1 #ifndef __ASM_SPINLOCK_H
2 #define __ASM_SPINLOCK_H
4 #include <asm/atomic.h>
5 #include <asm/rwlock.h>
7 #include <linux/compiler.h>
10 * Your basic SMP spinlocks, allowing only a single CPU anywhere
12 * Simple spin lock operations. There are two variants, one clears IRQ's
13 * on the local processor, one does not.
15 * We make no fairness assumptions. They have a cost.
17 * (the type definitions are in asm/spinlock_types.h)
20 #define __raw_spin_is_locked(x) \
21 (*(volatile signed char *)(&(x)->slock) <= 0)
23 #define __raw_spin_lock_string \
25 "lock ; decb %0\n\t" \
35 * NOTE: there's an irqs-on section here, which normally would have to be
36 * irq-traced, but on CONFIG_TRACE_IRQFLAGS we never use
37 * __raw_spin_lock_string_flags().
39 #define __raw_spin_lock_string_flags \
41 "lock ; decb %0\n\t" \
44 "testl $0x200, %1\n\t" \
60 #define __raw_spin_lock_string_up \
63 static inline void __raw_spin_lock(raw_spinlock_t *lock)
66 __raw_spin_lock_string,
67 __raw_spin_lock_string_up,
68 "=m" (lock->slock) : : "memory");
71 static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
74 __raw_spin_lock_string_flags,
75 __raw_spin_lock_string_up,
76 "=m" (lock->slock) : "r" (flags) : "memory");
79 static inline int __raw_spin_trylock(raw_spinlock_t *lock)
84 :"=q" (oldval), "=m" (lock->slock)
90 * __raw_spin_unlock based on writing $1 to the low byte.
91 * This method works. Despite all the confusion.
92 * (except on PPro SMP or if we are using OOSTORE, so we use xchgb there)
93 * (PPro errata 66, 92)
96 #if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
98 #define __raw_spin_unlock_string \
100 :"=m" (lock->slock) : : "memory"
103 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
105 __asm__ __volatile__(
106 __raw_spin_unlock_string
112 #define __raw_spin_unlock_string \
114 :"=q" (oldval), "=m" (lock->slock) \
115 :"0" (oldval) : "memory"
117 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
121 __asm__ __volatile__(
122 __raw_spin_unlock_string
128 #define __raw_spin_unlock_wait(lock) \
129 do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
132 * Read-write spinlocks, allowing multiple readers
133 * but only one writer.
135 * NOTE! it is quite common to have readers in interrupts
136 * but no interrupt writers. For those circumstances we
137 * can "mix" irq-safe locks - any writer needs to get a
138 * irq-safe write-lock, but readers can get non-irqsafe
141 * On x86, we implement read-write locks as a 32-bit counter
142 * with the high bit (sign) being the "contended" bit.
144 * The inline assembly is non-obvious. Think about it.
146 * Changed to use the same technique as rw semaphores. See
147 * semaphore.h for details. -ben
149 * the helpers are in arch/i386/kernel/semaphore.c
153 * read_can_lock - would read_trylock() succeed?
154 * @lock: the rwlock in question.
156 #define __raw_read_can_lock(x) ((int)(x)->lock > 0)
159 * write_can_lock - would write_trylock() succeed?
160 * @lock: the rwlock in question.
162 #define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
164 static inline void __raw_read_lock(raw_rwlock_t *rw)
166 __build_read_lock(rw, "__read_lock_failed");
169 static inline void __raw_write_lock(raw_rwlock_t *rw)
171 __build_write_lock(rw, "__write_lock_failed");
174 static inline int __raw_read_trylock(raw_rwlock_t *lock)
176 atomic_t *count = (atomic_t *)lock;
178 if (atomic_read(count) >= 0)
184 static inline int __raw_write_trylock(raw_rwlock_t *lock)
186 atomic_t *count = (atomic_t *)lock;
187 if (atomic_sub_and_test(RW_LOCK_BIAS, count))
189 atomic_add(RW_LOCK_BIAS, count);
193 static inline void __raw_read_unlock(raw_rwlock_t *rw)
195 asm volatile(LOCK_PREFIX "incl %0" :"=m" (rw->lock) : : "memory");
198 static inline void __raw_write_unlock(raw_rwlock_t *rw)
200 asm volatile(LOCK_PREFIX "addl $" RW_LOCK_BIAS_STR ", %0"
201 : "=m" (rw->lock) : : "memory");
204 #endif /* __ASM_SPINLOCK_H */