2 * ColdFire Internal Memory Map and Defines
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/immap_5249.h>
31 #include <asm/m5249.h>
33 #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
35 #define CFG_INTR_BASE (MMAP_INTC)
36 #define CFG_NUM_IRQS (64)
40 #define CFG_UDELAY_BASE (MMAP_DTMR0)
41 #define CFG_TMR_BASE (MMAP_DTMR1)
42 #define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
43 #define CFG_TMRINTR_NO (31)
44 #define CFG_TMRINTR_MASK (0x00000400)
45 #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
46 #define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
47 #define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
49 #endif /* CONFIG_M5249 */
52 #include <asm/immap_5253.h>
53 #include <asm/m5249.h>
54 #include <asm/m5253.h>
56 #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
58 #define CFG_INTR_BASE (MMAP_INTC)
59 #define CFG_NUM_IRQS (64)
63 #define CFG_UDELAY_BASE (MMAP_DTMR0)
64 #define CFG_TMR_BASE (MMAP_DTMR1)
65 #define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
66 #define CFG_TMRINTR_NO (27)
67 #define CFG_TMRINTR_MASK (0x00000400)
68 #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
69 #define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
70 #define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
72 #endif /* CONFIG_M5253 */
75 #include <asm/immap_5271.h>
76 #include <asm/m5271.h>
78 #define CFG_FEC0_IOBASE (MMAP_FEC)
79 #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
83 #define CFG_UDELAY_BASE (MMAP_DTMR0)
84 #define CFG_TMR_BASE (MMAP_DTMR3)
85 #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
86 #define CFG_TMRINTR_NO (INT0_LO_DTMR3)
87 #define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
88 #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
89 #define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */
90 #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
93 #define CFG_INTR_BASE (MMAP_INTC0)
94 #define CFG_NUM_IRQS (128)
95 #endif /* CONFIG_M5271 */
98 #include <asm/immap_5272.h>
99 #include <asm/m5272.h>
101 #define CFG_FEC0_IOBASE (MMAP_FEC)
102 #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
104 #define CFG_INTR_BASE (MMAP_INTC)
105 #define CFG_NUM_IRQS (64)
109 #define CFG_UDELAY_BASE (MMAP_TMR0)
110 #define CFG_TMR_BASE (MMAP_TMR3)
111 #define CFG_TMRPND_REG (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr)
112 #define CFG_TMRINTR_NO (INT_TMR3)
113 #define CFG_TMRINTR_MASK (INT_ISR_INT24)
114 #define CFG_TMRINTR_PEND (0)
115 #define CFG_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
116 #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
118 #endif /* CONFIG_M5272 */
121 #include <asm/immap_5282.h>
122 #include <asm/m5282.h>
124 #define CFG_FEC0_IOBASE (MMAP_FEC)
125 #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
127 #define CFG_INTR_BASE (MMAP_INTC0)
128 #define CFG_NUM_IRQS (128)
132 #define CFG_UDELAY_BASE (MMAP_DTMR0)
133 #define CFG_TMR_BASE (MMAP_DTMR3)
134 #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
135 #define CFG_TMRINTR_NO (INT0_LO_DTMR3)
136 #define CFG_TMRINTR_MASK (1 << INT0_LO_DTMR3)
137 #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
138 #define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
139 #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
141 #endif /* CONFIG_M5282 */
144 #include <asm/immap_5329.h>
145 #include <asm/m5329.h>
147 #define CFG_FEC0_IOBASE (MMAP_FEC)
148 #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
149 #define CFG_MCFRTC_BASE (MMAP_RTC)
153 #define CFG_UDELAY_BASE (MMAP_DTMR0)
154 #define CFG_TMR_BASE (MMAP_DTMR1)
155 #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
156 #define CFG_TMRINTR_NO (INT0_HI_DTMR1)
157 #define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
158 #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
159 #define CFG_TMRINTR_PRI (6)
160 #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
164 #define CFG_UDELAY_BASE (MMAP_PIT0)
165 #define CFG_PIT_BASE (MMAP_PIT1)
166 #define CFG_PIT_PRESCALE (6)
169 #define CFG_INTR_BASE (MMAP_INTC0)
170 #define CFG_NUM_IRQS (128)
171 #endif /* CONFIG_M5329 */
174 #include <asm/immap_5445x.h>
175 #include <asm/m5445x.h>
177 #define CFG_FEC0_IOBASE (MMAP_FEC0)
178 #define CFG_FEC1_IOBASE (MMAP_FEC1)
180 #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
182 #define CFG_MCFRTC_BASE (MMAP_RTC)
186 #define CFG_UDELAY_BASE (MMAP_DTMR0)
187 #define CFG_TMR_BASE (MMAP_DTMR1)
188 #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
189 #define CFG_TMRINTR_NO (INT0_HI_DTMR1)
190 #define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
191 #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
192 #define CFG_TMRINTR_PRI (6)
193 #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
197 #define CFG_UDELAY_BASE (MMAP_PIT0)
198 #define CFG_PIT_BASE (MMAP_PIT1)
199 #define CFG_PIT_PRESCALE (6)
202 #define CFG_INTR_BASE (MMAP_INTC0)
203 #define CFG_NUM_IRQS (128)
206 #define CFG_PCI_BAR0 CFG_SDRAM_BASE
207 #define CFG_PCI_BAR4 CFG_SDRAM_BASE
208 #define CFG_PCI_TBATR0 (CFG_SDRAM_BASE)
209 #define CFG_PCI_TBATR4 (CFG_SDRAM_BASE)
211 #endif /* CONFIG_M54455 */
213 #endif /* __IMMAP_H */