include/asm-mips/processor.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 Waldorf GMBH
   7  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
   8  * Copyright (C) 1996 Paul M. Antoine
   9  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  10  */
  11 #ifndef _ASM_PROCESSOR_H
  12 #define _ASM_PROCESSOR_H
  13
  14 #include <linux/cpumask.h>
  15 #include <linux/threads.h>
  16
  17 #include <asm/cachectl.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpu-info.h>
  20 #include <asm/mipsregs.h>
  21 #include <asm/prefetch.h>
  22 #include <asm/system.h>
  23
  24 /*
  25  * Return current * instruction pointer ("program counter").
  26  */
  27 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  28
  29 /*
  30  * System setup and hardware flags..
  31  */
  32 extern void (*cpu_wait)(void);
  33
  34 extern unsigned int vced_count, vcei_count;
  35
  36 #ifdef CONFIG_32BIT
  37 /*
  38  * User space process size: 2GB. This is hardcoded into a few places,
  39  * so don't change it unless you know what you are doing.
  40  */
  41 #define TASK_SIZE       0x7fff8000UL
  42
  43 /*
  44  * This decides where the kernel will search for a free chunk of vm
  45  * space during mmap's.
  46  */
  47 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
  48 #endif
  49
  50 #ifdef CONFIG_64BIT
  51 /*
  52  * User space process size: 1TB. This is hardcoded into a few places,
  53  * so don't change it unless you know what you are doing.  TASK_SIZE
  54  * is limited to 1TB by the R4000 architecture; R10000 and better can
  55  * support 16TB; the architectural reserve for future expansion is
  56  * 8192EB ...
  57  */
  58 #define TASK_SIZE32     0x7fff8000UL
  59 #define TASK_SIZE       0x10000000000UL
  60
  61 /*
  62  * This decides where the kernel will search for a free chunk of vm
  63  * space during mmap's.
  64  */
  65 #define TASK_UNMAPPED_BASE                                              \
  66         (test_thread_flag(TIF_32BIT_ADDR) ?                             \
  67                 PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
  68 #define TASK_SIZE_OF(tsk)                                               \
  69         (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
  70 #endif
  71
  72 #define NUM_FPU_REGS    32
  73
  74 typedef __u64 fpureg_t;
  75
  76 /*
  77  * It would be nice to add some more fields for emulator statistics, but there
  78  * are a number of fixed offsets in offset.h and elsewhere that would have to
  79  * be recalculated by hand.  So the additional information will be private to
  80  * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
  81  */
  82
  83 struct mips_fpu_struct {
  84         fpureg_t        fpr[NUM_FPU_REGS];
  85         unsigned int    fcr31;
  86 };
  87
  88 #define NUM_DSP_REGS   6
  89
  90 typedef __u32 dspreg_t;
  91
  92 struct mips_dsp_state {
  93         dspreg_t        dspr[NUM_DSP_REGS];
  94         unsigned int    dspcontrol;
  95 };
  96
  97 #define INIT_CPUMASK { \
  98         {0,} \
  99 }
 100
 101 typedef struct {
 102         unsigned long seg;
 103 } mm_segment_t;
 104
 105 #define ARCH_MIN_TASKALIGN      8
 106
 107 struct mips_abi;
 108
 109 /*
 110  * If you change thread_struct remember to change the #defines below too!
 111  */
 112 struct thread_struct {
 113         /* Saved main processor registers. */
 114         unsigned long reg16;
 115         unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
 116         unsigned long reg29, reg30, reg31;
 117
 118         /* Saved cp0 stuff. */
 119         unsigned long cp0_status;
 120
 121         /* Saved fpu/fpu emulator stuff. */
 122         struct mips_fpu_struct fpu;
 123 #ifdef CONFIG_MIPS_MT_FPAFF
 124         /* Emulated instruction count */
 125         unsigned long emulated_fp;
 126         /* Saved per-thread scheduler affinity mask */
 127         cpumask_t user_cpus_allowed;
 128 #endif /* CONFIG_MIPS_MT_FPAFF */
 129
 130         /* Saved state of the DSP ASE, if available. */
 131         struct mips_dsp_state dsp;
 132
 133         /* Other stuff associated with the thread. */
 134         unsigned long cp0_badvaddr;     /* Last user fault */
 135         unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
 136         unsigned long error_code;
 137         unsigned long trap_no;
 138         unsigned long irix_trampoline;  /* Wheee... */
 139         unsigned long irix_oldctx;
 140         struct mips_abi *abi;
 141 };
 142
 143 #ifdef CONFIG_MIPS_MT_FPAFF
 144 #define FPAFF_INIT                                              \
 145         .emulated_fp                    = 0,                    \
 146         .user_cpus_allowed              = INIT_CPUMASK,
 147 #else
 148 #define FPAFF_INIT
 149 #endif /* CONFIG_MIPS_MT_FPAFF */
 150
 151 #define INIT_THREAD  {                                          \
 152         /*                                                      \
 153          * Saved main processor registers                       \
 154          */                                                     \
 155         .reg16                  = 0,                            \
 156         .reg17                  = 0,                            \
 157         .reg18                  = 0,                            \
 158         .reg19                  = 0,                            \
 159         .reg20                  = 0,                            \
 160         .reg21                  = 0,                            \
 161         .reg22                  = 0,                            \
 162         .reg23                  = 0,                            \
 163         .reg29                  = 0,                            \
 164         .reg30                  = 0,                            \
 165         .reg31                  = 0,                            \
 166         /*                                                      \
 167          * Saved cp0 stuff                                      \
 168          */                                                     \
 169         .cp0_status             = 0,                            \
 170         /*                                                      \
 171          * Saved FPU/FPU emulator stuff                         \
 172          */                                                     \
 173         .fpu                    = {                             \
 174                 .fpr            = {0,},                         \
 175                 .fcr31          = 0,                            \
 176         },                                                      \
 177         /*                                                      \
 178          * FPU affinity state (null if not FPAFF)               \
 179          */                                                     \
 180         FPAFF_INIT                                              \
 181         /*                                                      \
 182          * Saved DSP stuff                                      \
 183          */                                                     \
 184         .dsp                    = {                             \
 185                 .dspr           = {0, },                        \
 186                 .dspcontrol     = 0,                            \
 187         },                                                      \
 188         /*                                                      \
 189          * Other stuff associated with the process              \
 190          */                                                     \
 191         .cp0_badvaddr           = 0,                            \
 192         .cp0_baduaddr           = 0,                            \
 193         .error_code             = 0,                            \
 194         .trap_no                = 0,                            \
 195         .irix_trampoline        = 0,                            \
 196         .irix_oldctx            = 0,                            \
 197 }
 198
 199 struct task_struct;
 200
 201 /* Free all resources held by a thread. */
 202 #define release_thread(thread) do { } while(0)
 203
 204 /* Prepare to copy thread state - unlazy all lazy status */
 205 #define prepare_to_copy(tsk)    do { } while (0)
 206
 207 extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 208
 209 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 210
 211 /*
 212  * Do necessary setup to start up a newly executed thread.
 213  */
 214 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
 215
 216 unsigned long get_wchan(struct task_struct *p);
 217
 218 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + THREAD_SIZE - 32)
 219 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk) - 1)
 220 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
 221 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
 222 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
 223
 224 #define cpu_relax()     barrier()
 225
 226 /*
 227  * Return_address is a replacement for __builtin_return_address(count)
 228  * which on certain architectures cannot reasonably be implemented in GCC
 229  * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
 230  * Note that __builtin_return_address(x>=1) is forbidden because GCC
 231  * aborts compilation on some CPUs.  It's simply not possible to unwind
 232  * some CPU's stackframes.
 233  *
 234  * __builtin_return_address works only for non-leaf functions.  We avoid the
 235  * overhead of a function call by forcing the compiler to save the return
 236  * address register on the stack.
 237  */
 238 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
 239
 240 #ifdef CONFIG_CPU_HAS_PREFETCH
 241
 242 #define ARCH_HAS_PREFETCH
 243
 244 static inline void prefetch(const void *addr)
 245 {
 246         __asm__ __volatile__(
 247         "       .set    mips4           \n"
 248         "       pref    %0, (%1)        \n"
 249         "       .set    mips0           \n"
 250         :
 251         : "i" (Pref_Load), "r" (addr));
 252 }
 253
 254 #endif
 255
 256 #endif /* _ASM_PROCESSOR_H */