include/asm-mips/system.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
   7  * Copyright (C) 1996 by Paul M. Antoine
   8  * Copyright (C) 1999 Silicon Graphics
   9  * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000 MIPS Technologies, Inc.
  11  */
  12 #ifndef _ASM_SYSTEM_H
  13 #define _ASM_SYSTEM_H
  14
  15 #include <linux/config.h>
  16 #include <linux/types.h>
  17
  18 #include <asm/addrspace.h>
  19 #include <asm/cpu-features.h>
  20 #include <asm/dsp.h>
  21 #include <asm/ptrace.h>
  22 #include <asm/war.h>
  23 #include <asm/interrupt.h>
  24
  25 /*
  26  * read_barrier_depends - Flush all pending reads that subsequents reads
  27  * depend on.
  28  *
  29  * No data-dependent reads from memory-like regions are ever reordered
  30  * over this barrier.  All reads preceding this primitive are guaranteed
  31  * to access memory (but not necessarily other CPUs' caches) before any
  32  * reads following this primitive that depend on the data return by
  33  * any of the preceding reads.  This primitive is much lighter weight than
  34  * rmb() on most CPUs, and is never heavier weight than is
  35  * rmb().
  36  *
  37  * These ordering constraints are respected by both the local CPU
  38  * and the compiler.
  39  *
  40  * Ordering is not guaranteed by anything other than these primitives,
  41  * not even by data dependencies.  See the documentation for
  42  * memory_barrier() for examples and URLs to more information.
  43  *
  44  * For example, the following code would force ordering (the initial
  45  * value of "a" is zero, "b" is one, and "p" is "&a"):
  46  *
  47  * <programlisting>
  48  *      CPU 0                           CPU 1
  49  *
  50  *      b = 2;
  51  *      memory_barrier();
  52  *      p = &b;                         q = p;
  53  *                                      read_barrier_depends();
  54  *                                      d = *q;
  55  * </programlisting>
  56  *
  57  * because the read of "*q" depends on the read of "p" and these
  58  * two reads are separated by a read_barrier_depends().  However,
  59  * the following code, with the same initial values for "a" and "b":
  60  *
  61  * <programlisting>
  62  *      CPU 0                           CPU 1
  63  *
  64  *      a = 2;
  65  *      memory_barrier();
  66  *      b = 3;                          y = b;
  67  *                                      read_barrier_depends();
  68  *                                      x = a;
  69  * </programlisting>
  70  *
  71  * does not enforce ordering, since there is no data dependency between
  72  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
  73  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
  74  * in cases like this where there are no data dependencies.
  75  */
  76
  77 #define read_barrier_depends()  do { } while(0)
  78
  79 #ifdef CONFIG_CPU_HAS_SYNC
  80 #define __sync()                                \
  81         __asm__ __volatile__(                   \
  82                 ".set   push\n\t"               \
  83                 ".set   noreorder\n\t"          \
  84                 ".set   mips2\n\t"              \
  85                 "sync\n\t"                      \
  86                 ".set   pop"                    \
  87                 : /* no output */               \
  88                 : /* no input */                \
  89                 : "memory")
  90 #else
  91 #define __sync()        do { } while(0)
  92 #endif
  93
  94 #define __fast_iob()                            \
  95         __asm__ __volatile__(                   \
  96                 ".set   push\n\t"               \
  97                 ".set   noreorder\n\t"          \
  98                 "lw     $0,%0\n\t"              \
  99                 "nop\n\t"                       \
 100                 ".set   pop"                    \
 101                 : /* no output */               \
 102                 : "m" (*(int *)CKSEG1)          \
 103                 : "memory")
 104
 105 #define fast_wmb()      __sync()
 106 #define fast_rmb()      __sync()
 107 #define fast_mb()       __sync()
 108 #define fast_iob()                              \
 109         do {                                    \
 110                 __sync();                       \
 111                 __fast_iob();                   \
 112         } while (0)
 113
 114 #ifdef CONFIG_CPU_HAS_WB
 115
 116 #include <asm/wbflush.h>
 117
 118 #define wmb()           fast_wmb()
 119 #define rmb()           fast_rmb()
 120 #define mb()            wbflush()
 121 #define iob()           wbflush()
 122
 123 #else /* !CONFIG_CPU_HAS_WB */
 124
 125 #define wmb()           fast_wmb()
 126 #define rmb()           fast_rmb()
 127 #define mb()            fast_mb()
 128 #define iob()           fast_iob()
 129
 130 #endif /* !CONFIG_CPU_HAS_WB */
 131
 132 #ifdef CONFIG_SMP
 133 #define smp_mb()        mb()
 134 #define smp_rmb()       rmb()
 135 #define smp_wmb()       wmb()
 136 #define smp_read_barrier_depends()      read_barrier_depends()
 137 #else
 138 #define smp_mb()        barrier()
 139 #define smp_rmb()       barrier()
 140 #define smp_wmb()       barrier()
 141 #define smp_read_barrier_depends()      do { } while(0)
 142 #endif
 143
 144 #define set_mb(var, value) \
 145 do { var = value; mb(); } while (0)
 146
 147 #define set_wmb(var, value) \
 148 do { var = value; wmb(); } while (0)
 149
 150 /*
 151  * switch_to(n) should switch tasks to task nr n, first
 152  * checking that n isn't the current task, in which case it does nothing.
 153  */
 154 extern asmlinkage void *resume(void *last, void *next, void *next_ti);
 155
 156 struct task_struct;
 157
 158 #define switch_to(prev,next,last)                                       \
 159 do {                                                                    \
 160         if (cpu_has_dsp)                                                \
 161                 __save_dsp(prev);                                       \
 162         (last) = resume(prev, next, next->thread_info);                 \
 163         if (cpu_has_dsp)                                                \
 164                 __restore_dsp(current);                                 \
 165 } while(0)
 166
 167 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
 168 {
 169         __u32 retval;
 170
 171         if (cpu_has_llsc && R10000_LLSC_WAR) {
 172                 unsigned long dummy;
 173
 174                 __asm__ __volatile__(
 175                 "       .set    mips3                                   \n"
 176                 "1:     ll      %0, %3                  # xchg_u32      \n"
 177                 "       .set    mips0                                   \n"
 178                 "       move    %2, %z4                                 \n"
 179                 "       .set    mips3                                   \n"
 180                 "       sc      %2, %1                                  \n"
 181                 "       beqzl   %2, 1b                                  \n"
 182 #ifdef CONFIG_SMP
 183                 "       sync                                            \n"
 184 #endif
 185                 "       .set    mips0                                   \n"
 186                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 187                 : "R" (*m), "Jr" (val)
 188                 : "memory");
 189         } else if (cpu_has_llsc) {
 190                 unsigned long dummy;
 191
 192                 __asm__ __volatile__(
 193                 "       .set    mips3                                   \n"
 194                 "1:     ll      %0, %3                  # xchg_u32      \n"
 195                 "       .set    mips0                                   \n"
 196                 "       move    %2, %z4                                 \n"
 197                 "       .set    mips3                                   \n"
 198                 "       sc      %2, %1                                  \n"
 199                 "       beqz    %2, 1b                                  \n"
 200 #ifdef CONFIG_SMP
 201                 "       sync                                            \n"
 202 #endif
 203                 "       .set    mips0                                   \n"
 204                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 205                 : "R" (*m), "Jr" (val)
 206                 : "memory");
 207         } else {
 208                 unsigned long flags;
 209
 210                 local_irq_save(flags);
 211                 retval = *m;
 212                 *m = val;
 213                 local_irq_restore(flags);       /* implies memory barrier  */
 214         }
 215
 216         return retval;
 217 }
 218
 219 #ifdef CONFIG_64BIT
 220 static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 221 {
 222         __u64 retval;
 223
 224         if (cpu_has_llsc && R10000_LLSC_WAR) {
 225                 unsigned long dummy;
 226
 227                 __asm__ __volatile__(
 228                 "       .set    mips3                                   \n"
 229                 "1:     lld     %0, %3                  # xchg_u64      \n"
 230                 "       move    %2, %z4                                 \n"
 231                 "       scd     %2, %1                                  \n"
 232                 "       beqzl   %2, 1b                                  \n"
 233 #ifdef CONFIG_SMP
 234                 "       sync                                            \n"
 235 #endif
 236                 "       .set    mips0                                   \n"
 237                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 238                 : "R" (*m), "Jr" (val)
 239                 : "memory");
 240         } else if (cpu_has_llsc) {
 241                 unsigned long dummy;
 242
 243                 __asm__ __volatile__(
 244                 "       .set    mips3                                   \n"
 245                 "1:     lld     %0, %3                  # xchg_u64      \n"
 246                 "       move    %2, %z4                                 \n"
 247                 "       scd     %2, %1                                  \n"
 248                 "       beqz    %2, 1b                                  \n"
 249 #ifdef CONFIG_SMP
 250                 "       sync                                            \n"
 251 #endif
 252                 "       .set    mips0                                   \n"
 253                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 254                 : "R" (*m), "Jr" (val)
 255                 : "memory");
 256         } else {
 257                 unsigned long flags;
 258
 259                 local_irq_save(flags);
 260                 retval = *m;
 261                 *m = val;
 262                 local_irq_restore(flags);       /* implies memory barrier  */
 263         }
 264
 265         return retval;
 266 }
 267 #else
 268 extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
 269 #define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
 270 #endif
 271
 272 /* This function doesn't exist, so you'll get a linker error
 273    if something tries to do an invalid xchg().  */
 274 extern void __xchg_called_with_bad_pointer(void);
 275
 276 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 277 {
 278         switch (size) {
 279                 case 4:
 280                         return __xchg_u32(ptr, x);
 281                 case 8:
 282                         return __xchg_u64(ptr, x);
 283         }
 284         __xchg_called_with_bad_pointer();
 285         return x;
 286 }
 287
 288 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 289 #define tas(ptr) (xchg((ptr),1))
 290
 291 #define __HAVE_ARCH_CMPXCHG 1
 292
 293 static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
 294         unsigned long new)
 295 {
 296         __u32 retval;
 297
 298         if (cpu_has_llsc && R10000_LLSC_WAR) {
 299                 __asm__ __volatile__(
 300                 "       .set    push                                    \n"
 301                 "       .set    noat                                    \n"
 302                 "       .set    mips3                                   \n"
 303                 "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
 304                 "       bne     %0, %z3, 2f                             \n"
 305                 "       .set    mips0                                   \n"
 306                 "       move    $1, %z4                                 \n"
 307                 "       .set    mips3                                   \n"
 308                 "       sc      $1, %1                                  \n"
 309                 "       beqzl   $1, 1b                                  \n"
 310 #ifdef CONFIG_SMP
 311                 "       sync                                            \n"
 312 #endif
 313                 "2:                                                     \n"
 314                 "       .set    pop                                     \n"
 315                 : "=&r" (retval), "=m" (*m)
 316                 : "R" (*m), "Jr" (old), "Jr" (new)
 317                 : "memory");
 318         } else if (cpu_has_llsc) {
 319                 __asm__ __volatile__(
 320                 "       .set    push                                    \n"
 321                 "       .set    noat                                    \n"
 322                 "       .set    mips3                                   \n"
 323                 "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
 324                 "       bne     %0, %z3, 2f                             \n"
 325                 "       .set    mips0                                   \n"
 326                 "       move    $1, %z4                                 \n"
 327                 "       .set    mips3                                   \n"
 328                 "       sc      $1, %1                                  \n"
 329                 "       beqz    $1, 1b                                  \n"
 330 #ifdef CONFIG_SMP
 331                 "       sync                                            \n"
 332 #endif
 333                 "2:                                                     \n"
 334                 "       .set    pop                                     \n"
 335                 : "=&r" (retval), "=m" (*m)
 336                 : "R" (*m), "Jr" (old), "Jr" (new)
 337                 : "memory");
 338         } else {
 339                 unsigned long flags;
 340
 341                 local_irq_save(flags);
 342                 retval = *m;
 343                 if (retval == old)
 344                         *m = new;
 345                 local_irq_restore(flags);       /* implies memory barrier  */
 346         }
 347
 348         return retval;
 349 }
 350
 351 #ifdef CONFIG_64BIT
 352 static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
 353         unsigned long new)
 354 {
 355         __u64 retval;
 356
 357         if (cpu_has_llsc) {
 358                 __asm__ __volatile__(
 359                 "       .set    push                                    \n"
 360                 "       .set    noat                                    \n"
 361                 "       .set    mips3                                   \n"
 362                 "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
 363                 "       bne     %0, %z3, 2f                             \n"
 364                 "       move    $1, %z4                                 \n"
 365                 "       scd     $1, %1                                  \n"
 366                 "       beqzl   $1, 1b                                  \n"
 367 #ifdef CONFIG_SMP
 368                 "       sync                                            \n"
 369 #endif
 370                 "2:                                                     \n"
 371                 "       .set    pop                                     \n"
 372                 : "=&r" (retval), "=m" (*m)
 373                 : "R" (*m), "Jr" (old), "Jr" (new)
 374                 : "memory");
 375         } else if (cpu_has_llsc) {
 376                 __asm__ __volatile__(
 377                 "       .set    push                                    \n"
 378                 "       .set    noat                                    \n"
 379                 "       .set    mips3                                   \n"
 380                 "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
 381                 "       bne     %0, %z3, 2f                             \n"
 382                 "       move    $1, %z4                                 \n"
 383                 "       scd     $1, %1                                  \n"
 384                 "       beqz    $1, 1b                                  \n"
 385 #ifdef CONFIG_SMP
 386                 "       sync                                            \n"
 387 #endif
 388                 "2:                                                     \n"
 389                 "       .set    pop                                     \n"
 390                 : "=&r" (retval), "=m" (*m)
 391                 : "R" (*m), "Jr" (old), "Jr" (new)
 392                 : "memory");
 393         } else {
 394                 unsigned long flags;
 395
 396                 local_irq_save(flags);
 397                 retval = *m;
 398                 if (retval == old)
 399                         *m = new;
 400                 local_irq_restore(flags);       /* implies memory barrier  */
 401         }
 402
 403         return retval;
 404 }
 405 #else
 406 extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
 407         volatile int * m, unsigned long old, unsigned long new);
 408 #define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
 409 #endif
 410
 411 /* This function doesn't exist, so you'll get a linker error
 412    if something tries to do an invalid cmpxchg().  */
 413 extern void __cmpxchg_called_with_bad_pointer(void);
 414
 415 static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
 416         unsigned long new, int size)
 417 {
 418         switch (size) {
 419         case 4:
 420                 return __cmpxchg_u32(ptr, old, new);
 421         case 8:
 422                 return __cmpxchg_u64(ptr, old, new);
 423         }
 424         __cmpxchg_called_with_bad_pointer();
 425         return old;
 426 }
 427
 428 #define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
 429
 430 extern void set_handler (unsigned long offset, void *addr, unsigned long len);
 431 extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
 432 extern void *set_vi_handler (int n, void *addr);
 433 extern void *set_vi_srs_handler (int n, void *addr, int regset);
 434 extern void *set_except_vector(int n, void *addr);
 435 extern void per_cpu_trap_init(void);
 436
 437 extern NORET_TYPE void die(const char *, struct pt_regs *);
 438
 439 static inline void die_if_kernel(const char *str, struct pt_regs *regs)
 440 {
 441         if (unlikely(!user_mode(regs)))
 442                 die(str, regs);
 443 }
 444
 445 extern int stop_a_enabled;
 446
 447 /*
 448  * See include/asm-ia64/system.h; prevents deadlock on SMP
 449  * systems.
 450  */
 451 #define __ARCH_WANT_UNLOCKED_CTXSW
 452
 453 #define arch_align_stack(x) (x)
 454
 455 #endif /* _ASM_SYSTEM_H */