2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * C29XPCIE board configuration file
14 #define CONFIG_PHYS_64BIT
15 #define CONFIG_SYS_GENERIC_BOARD
16 #define CONFIG_DISPLAY_BOARDINFO
18 #ifdef CONFIG_C29XPCIE
19 #define CONFIG_PPC_C29X
22 #ifdef CONFIG_SPIFLASH
23 #define CONFIG_RAMBOOT_SPIFLASH
24 #define CONFIG_SYS_TEXT_BASE 0x11000000
25 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
29 #ifdef CONFIG_TPL_BUILD
30 #define CONFIG_SPL_NAND_BOOT
31 #define CONFIG_SPL_FLUSH_IMAGE
32 #define CONFIG_SPL_ENV_SUPPORT
33 #define CONFIG_SPL_NAND_INIT
34 #define CONFIG_SPL_SERIAL_SUPPORT
35 #define CONFIG_SPL_LIBGENERIC_SUPPORT
36 #define CONFIG_SPL_LIBCOMMON_SUPPORT
37 #define CONFIG_SPL_I2C_SUPPORT
38 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
39 #define CONFIG_SPL_NAND_SUPPORT
40 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
41 #define CONFIG_SPL_COMMON_INIT_DDR
42 #define CONFIG_SPL_MAX_SIZE (128 << 10)
43 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
44 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
45 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
46 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
47 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
48 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
49 #elif defined(CONFIG_SPL_BUILD)
50 #define CONFIG_SPL_INIT_MINIMAL
51 #define CONFIG_SPL_SERIAL_SUPPORT
52 #define CONFIG_SPL_NAND_SUPPORT
53 #define CONFIG_SPL_NAND_MINIMAL
54 #define CONFIG_SPL_FLUSH_IMAGE
55 #define CONFIG_SPL_TEXT_BASE 0xff800000
56 #define CONFIG_SPL_MAX_SIZE 8192
57 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
58 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
59 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
60 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
62 #define CONFIG_SPL_PAD_TO 0x20000
63 #define CONFIG_TPL_PAD_TO 0x20000
64 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
65 #define CONFIG_SYS_TEXT_BASE 0x11001000
66 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
69 #ifndef CONFIG_SYS_TEXT_BASE
70 #define CONFIG_SYS_TEXT_BASE 0xeff40000
73 #ifndef CONFIG_RESET_VECTOR_ADDRESS
74 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
77 #ifdef CONFIG_SPL_BUILD
78 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
80 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
83 #ifdef CONFIG_SPL_BUILD
84 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
87 /* High Level Configuration Options */
88 #define CONFIG_BOOKE /* BOOKE */
89 #define CONFIG_E500 /* BOOKE e500 family */
90 #define CONFIG_FSL_IFC /* Enable IFC Support */
91 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
92 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
94 #define CONFIG_PCI /* Enable PCI/PCIE */
96 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
97 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
98 #define CONFIG_PCI_INDIRECT_BRIDGE
99 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
100 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
102 #define CONFIG_CMD_NET
103 #define CONFIG_CMD_PCI
109 * Memory space is mapped 1-1, but I/O space must start from 0.
111 /* controller 1, Slot 1, tgtid 1, Base address a000 */
112 #define CONFIG_SYS_PCIE1_NAME "Slot 1"
113 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
114 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
115 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
116 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
117 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
118 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
119 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
120 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
122 #define CONFIG_PCI_PNP /* do pci plug-and-play */
124 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
125 #define CONFIG_DOS_PARTITION
128 #define CONFIG_FSL_LAW /* Use common FSL init code */
129 #define CONFIG_TSEC_ENET
130 #define CONFIG_ENV_OVERWRITE
132 #define CONFIG_DDR_CLK_FREQ 100000000
133 #define CONFIG_SYS_CLK_FREQ 66666666
135 #define CONFIG_HWCONFIG
138 * These can be toggled for performance analysis, otherwise use default.
140 #define CONFIG_L2_CACHE /* toggle L2 cache */
141 #define CONFIG_BTB /* toggle branch predition */
143 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
145 #define CONFIG_ENABLE_36BIT_PHYS
147 #define CONFIG_ADDR_MAP 1
148 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
150 #define CONFIG_SYS_MEMTEST_START 0x00200000
151 #define CONFIG_SYS_MEMTEST_END 0x00400000
152 #define CONFIG_PANIC_HANG
155 #define CONFIG_SYS_FSL_DDR3
156 #define CONFIG_DDR_SPD
157 #define CONFIG_SYS_SPD_BUS_NUM 0
158 #define SPD_EEPROM_ADDRESS 0x50
159 #define CONFIG_SYS_DDR_RAW_TIMING
162 #define CONFIG_DDR_ECC
163 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
164 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
166 #define CONFIG_SYS_SDRAM_SIZE 512
167 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
168 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
170 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
171 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
173 #define CONFIG_SYS_CCSRBAR 0xffe00000
174 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
176 /* Platform SRAM setting */
177 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
178 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
179 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
180 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
182 #ifdef CONFIG_SPL_BUILD
183 #define CONFIG_SYS_NO_FLASH
189 /* NOR Flash on IFC */
190 #define CONFIG_SYS_FLASH_BASE 0xec000000
191 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
193 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
195 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
196 #define CONFIG_SYS_MAX_FLASH_BANKS 1
198 #define CONFIG_SYS_FLASH_QUIET_TEST
199 #define CONFIG_FLASH_SHOW_PROGRESS 45
200 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
201 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
203 /* 16Bit NOR Flash - S29GL512S10TFI01 */
204 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
205 CSPR_PORT_SIZE_16 | \
208 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
209 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
211 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
212 FTIM0_NOR_TEADC(0x5) | \
213 FTIM0_NOR_TEAHC(0x5))
214 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
215 FTIM1_NOR_TRAD_NOR(0x1A) |\
216 FTIM1_NOR_TSEQRAD_NOR(0x13))
217 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
218 FTIM2_NOR_TCH(0x4) | \
219 FTIM2_NOR_TWPH(0x0E) | \
221 #define CONFIG_SYS_NOR_FTIM3 0x0
223 /* CFI for NOR Flash */
224 #define CONFIG_FLASH_CFI_DRIVER
225 #define CONFIG_SYS_FLASH_CFI
226 #define CONFIG_SYS_FLASH_EMPTY_INFO
227 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
229 /* NAND Flash on IFC */
230 #define CONFIG_NAND_FSL_IFC
231 #define CONFIG_SYS_NAND_BASE 0xff800000
232 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
234 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
236 #define CONFIG_SYS_MAX_NAND_DEVICE 1
237 #define CONFIG_MTD_NAND_VERIFY_WRITE
238 #define CONFIG_CMD_NAND
239 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
241 /* 8Bit NAND Flash - K9F1G08U0B */
242 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
246 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
247 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
248 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
249 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
250 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
251 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
252 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
253 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
254 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
255 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
256 FTIM0_NAND_TWP(0x0c) | \
257 FTIM0_NAND_TWCHT(0x08) | \
258 FTIM0_NAND_TWH(0x06))
259 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
260 FTIM1_NAND_TWBE(0x1d) | \
261 FTIM1_NAND_TRR(0x08) | \
262 FTIM1_NAND_TRP(0x0c))
263 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
264 FTIM2_NAND_TREH(0x0a) | \
265 FTIM2_NAND_TWHRE(0x18))
266 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
268 #define CONFIG_SYS_NAND_DDR_LAW 11
270 /* Set up IFC registers for boot location NOR/NAND */
272 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
273 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
274 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
275 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
276 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
277 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
278 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
279 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
280 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
281 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
282 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
283 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
284 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
285 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
286 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
288 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
289 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
290 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
291 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
292 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
293 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
294 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
295 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
296 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
297 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
298 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
299 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
300 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
301 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
302 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
305 /* CPLD on IFC, selected by CS2 */
306 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
307 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
308 | CONFIG_SYS_CPLD_BASE)
310 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
314 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
315 #define CONFIG_SYS_CSOR2 0x0
316 /* CPLD Timing parameters for IFC CS2 */
317 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
318 FTIM0_GPCM_TEADC(0x0e) | \
319 FTIM0_GPCM_TEAHC(0x0e))
320 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
321 FTIM1_GPCM_TRAD(0x1f))
322 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
323 FTIM2_GPCM_TCH(0x8) | \
324 FTIM2_GPCM_TWP(0x1f))
325 #define CONFIG_SYS_CS2_FTIM3 0x0
327 #if defined(CONFIG_RAMBOOT_SPIFLASH)
328 #define CONFIG_SYS_RAMBOOT
329 #define CONFIG_SYS_EXTRA_ENV_RELOC
332 #define CONFIG_BOARD_EARLY_INIT_R
334 #define CONFIG_SYS_INIT_RAM_LOCK
335 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
336 #define CONFIG_SYS_INIT_RAM_END 0x00004000
338 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
339 - GENERATED_GBL_DATA_SIZE)
340 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
342 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
343 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
346 * Config the L2 Cache as L2 SRAM
348 #if defined(CONFIG_SPL_BUILD)
349 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
350 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
351 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
352 #define CONFIG_SYS_L2_SIZE (256 << 10)
353 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
354 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
355 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
356 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
357 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
358 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
359 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
360 #elif defined(CONFIG_NAND)
361 #ifdef CONFIG_TPL_BUILD
362 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
363 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
364 #define CONFIG_SYS_L2_SIZE (256 << 10)
365 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
366 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
367 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
368 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
369 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
370 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
372 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
373 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
374 #define CONFIG_SYS_L2_SIZE (256 << 10)
375 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
376 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
377 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
383 #define CONFIG_CONS_INDEX 1
384 #define CONFIG_SYS_NS16550
385 #define CONFIG_SYS_NS16550_SERIAL
386 #define CONFIG_SYS_NS16550_REG_SIZE 1
387 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
389 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
390 #define CONFIG_NS16550_MIN_FUNCTIONS
393 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
394 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
396 #define CONFIG_SYS_BAUDRATE_TABLE \
397 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
399 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
400 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
402 /* Use the HUSH parser */
403 #define CONFIG_SYS_HUSH_PARSER
406 * Pass open firmware flat tree
408 #define CONFIG_OF_LIBFDT
409 #define CONFIG_OF_BOARD_SETUP
410 #define CONFIG_OF_STDOUT_VIA_ALIAS
412 /* new uImage format support */
414 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
416 #define CONFIG_SYS_I2C
417 #define CONFIG_SYS_I2C_FSL
418 #define CONFIG_SYS_FSL_I2C_SPEED 400000
419 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
420 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
421 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
422 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
423 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
426 /* enable read and write access to EEPROM */
427 #define CONFIG_CMD_EEPROM
428 #define CONFIG_SYS_I2C_MULTI_EEPROMS
429 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
430 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
431 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
433 #define CONFIG_CMD_I2C
435 /* eSPI - Enhanced SPI */
436 #define CONFIG_FSL_ESPI
437 #define CONFIG_SPI_FLASH
438 #define CONFIG_SPI_FLASH_SPANSION
439 #define CONFIG_SPI_FLASH_EON
440 #define CONFIG_CMD_SF
441 #define CONFIG_SF_DEFAULT_SPEED 10000000
442 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
444 #ifdef CONFIG_TSEC_ENET
445 #define CONFIG_NET_MULTI
446 #define CONFIG_MII /* MII PHY management */
447 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
448 #define CONFIG_TSEC1 1
449 #define CONFIG_TSEC1_NAME "eTSEC1"
450 #define CONFIG_TSEC2 1
451 #define CONFIG_TSEC2_NAME "eTSEC2"
453 /* Default mode is RGMII mode */
454 #define TSEC1_PHY_ADDR 0
455 #define TSEC2_PHY_ADDR 2
457 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
458 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
460 #define CONFIG_ETHPRIME "eTSEC1"
462 #define CONFIG_PHY_GIGE
463 #endif /* CONFIG_TSEC_ENET */
468 #if defined(CONFIG_SYS_RAMBOOT)
469 #if defined(CONFIG_RAMBOOT_SPIFLASH)
470 #define CONFIG_ENV_IS_IN_SPI_FLASH
471 #define CONFIG_ENV_SPI_BUS 0
472 #define CONFIG_ENV_SPI_CS 0
473 #define CONFIG_ENV_SPI_MAX_HZ 10000000
474 #define CONFIG_ENV_SPI_MODE 0
475 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
476 #define CONFIG_ENV_SECT_SIZE 0x10000
477 #define CONFIG_ENV_SIZE 0x2000
479 #elif defined(CONFIG_NAND)
480 #define CONFIG_ENV_IS_IN_NAND
481 #ifdef CONFIG_TPL_BUILD
482 #define CONFIG_ENV_SIZE 0x2000
483 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
485 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
486 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
488 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
490 #define CONFIG_ENV_IS_IN_FLASH
491 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
492 #define CONFIG_ENV_SIZE 0x2000
493 #define CONFIG_ENV_SECT_SIZE 0x20000
496 #define CONFIG_LOADS_ECHO
497 #define CONFIG_SYS_LOADS_BAUD_CHANGE
500 * Command line configuration.
502 #include <config_cmd_default.h>
504 #define CONFIG_CMD_ERRATA
505 #define CONFIG_CMD_ELF
506 #define CONFIG_CMD_IRQ
507 #define CONFIG_CMD_MII
508 #define CONFIG_CMD_PING
509 #define CONFIG_CMD_SETEXPR
510 #define CONFIG_CMD_REGINFO
512 /* Hash command with SHA acceleration supported in hardware */
513 #ifdef CONFIG_FSL_CAAM
514 #define CONFIG_CMD_HASH
515 #define CONFIG_SHA_HW_ACCEL
519 * Miscellaneous configurable options
521 #define CONFIG_SYS_LONGHELP /* undef to save memory */
522 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
523 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
524 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
526 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
527 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
528 /* Print Buffer Size */
529 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
530 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
533 * For booting Linux, the board info and command line data
534 * have to be in the first 64 MB of memory, since this is
535 * the maximum mapped by the Linux kernel during initialization.
537 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
538 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
541 * Environment Configuration
544 #ifdef CONFIG_TSEC_ENET
545 #define CONFIG_HAS_ETH0
546 #define CONFIG_HAS_ETH1
549 #define CONFIG_ROOTPATH "/opt/nfsroot"
550 #define CONFIG_BOOTFILE "uImage"
551 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
553 /* default location for tftp and bootm */
554 #define CONFIG_LOADADDR 1000000
556 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
558 #define CONFIG_BAUDRATE 115200
560 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
562 #define CONFIG_EXTRA_ENV_SETTINGS \
563 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
565 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
566 "loadaddr=1000000\0" \
567 "consoledev=ttyS0\0" \
568 "ramdiskaddr=2000000\0" \
569 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
571 "fdtfile=name/of/device-tree.dtb\0" \
572 "othbootargs=ramdisk_size=600000\0" \
574 #define CONFIG_RAMBOOTCOMMAND \
575 "setenv bootargs root=/dev/ram rw " \
576 "console=$consoledev,$baudrate $othbootargs; " \
577 "tftp $ramdiskaddr $ramdiskfile;" \
578 "tftp $loadaddr $bootfile;" \
579 "tftp $fdtaddr $fdtfile;" \
580 "bootm $loadaddr $ramdiskaddr $fdtaddr"
582 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
584 #include <asm/fsl_secure_boot.h>
586 #endif /* __CONFIG_H */