2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37 #define CONFIG_CPU87 1 /* ...on a CPU87 board */
39 #define CONFIG_CPM2 1 /* Has a CPM2 */
42 * select serial console configuration
44 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
48 * if CONFIG_CONS_NONE is defined, then the serial console routines must
49 * defined elsewhere (for example, on the cogent platform, there are serial
50 * ports on the motherboard which are used for the serial console - see
51 * cogent/cma101/serial.[ch]).
53 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
54 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
55 #undef CONFIG_CONS_NONE /* define if console on something else*/
56 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
58 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
59 #define CONFIG_BAUDRATE 230400
61 #define CONFIG_BAUDRATE 9600
65 * select ethernet configuration
67 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
68 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
71 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
72 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
74 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
75 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
76 #undef CONFIG_ETHER_NONE /* define if ether on something else */
77 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
79 #define CONFIG_HAS_ETH1 1
80 #define CONFIG_HAS_ETH2 1
82 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
87 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
88 * - Enable Full Duplex in FSMR
90 # define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
91 # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
92 # define CFG_CPMFCR_RAMTYPE 0
93 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
95 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
100 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
101 * - Enable Full Duplex in FSMR
103 # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
104 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
105 # define CFG_CPMFCR_RAMTYPE 0
106 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
108 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
110 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
111 #define CONFIG_8260_CLKIN 100000000 /* in Hz */
113 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
115 #define CONFIG_PREBOOT \
117 "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \
120 #undef CONFIG_BOOTARGS
121 #define CONFIG_BOOTCOMMAND \
123 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
124 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
127 /*-----------------------------------------------------------------------
128 * I2C/EEPROM/RTC configuration
130 #define CONFIG_SOFT_I2C /* Software I2C support enabled */
132 # define CFG_I2C_SPEED 50000
133 # define CFG_I2C_SLAVE 0xFE
135 * Software (bit-bang) I2C driver configuration
137 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
138 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
139 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
140 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
141 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
142 else iop->pdat &= ~0x00010000
143 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
144 else iop->pdat &= ~0x00020000
145 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
147 #define CONFIG_RTC_PCF8563
148 #define CFG_I2C_RTC_ADDR 0x51
150 #undef CONFIG_WATCHDOG /* watchdog disabled */
152 /*-----------------------------------------------------------------------
153 * Disk-On-Chip configuration
156 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
158 #define CFG_DOC_SUPPORT_2000
159 #define CFG_DOC_SUPPORT_MILLENNIUM
161 /*-----------------------------------------------------------------------
162 * Miscellaneous configuration options
165 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
166 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
168 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
172 * Command line configuration.
174 #include <config_cmd_default.h>
176 #define CONFIG_CMD_BEDBUG
177 #define CONFIG_CMD_DATE
178 #define CONFIG_CMD_DOC
179 #define CONFIG_CMD_EEPROM
180 #define CONFIG_CMD_I2C
183 #define CONFIG_CMD_PCI
187 #define CFG_NAND_LEGACY
190 * Miscellaneous configurable options
192 #define CFG_LONGHELP /* undef to save memory */
193 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
194 #if defined(CONFIG_CMD_KGDB)
195 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
197 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
199 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
200 #define CFG_MAXARGS 16 /* max number of command args */
201 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
203 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
204 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
206 #define CFG_LOAD_ADDR 0x100000 /* default load address */
208 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
210 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
212 #define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */
217 * For booting Linux, the board info and command line data
218 * have to be in the first 8 MB of memory, since this is
219 * the maximum mapped by the Linux kernel during initialization.
221 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
223 /*-----------------------------------------------------------------------
224 * Flash configuration
227 #define CFG_BOOTROM_BASE 0xFF800000
228 #define CFG_BOOTROM_SIZE 0x00080000
229 #define CFG_FLASH_BASE 0xFF000000
230 #define CFG_FLASH_SIZE 0x00800000
232 /*-----------------------------------------------------------------------
235 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
236 #define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */
238 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
239 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
241 /*-----------------------------------------------------------------------
242 * Other areas to be mapped
245 /* CS3: Dual ported SRAM */
246 #define CFG_DPSRAM_BASE 0x40000000
247 #define CFG_DPSRAM_SIZE 0x00100000
249 /* CS4: DiskOnChip */
250 #define CFG_DOC_BASE 0xF4000000
251 #define CFG_DOC_SIZE 0x00100000
253 /* CS5: FDC37C78 controller */
254 #define CFG_FDC37C78_BASE 0xF1000000
255 #define CFG_FDC37C78_SIZE 0x00100000
257 /* CS6: Board configuration registers */
258 #define CFG_BCRS_BASE 0xF2000000
259 #define CFG_BCRS_SIZE 0x00010000
261 /* CS7: VME Extended Access Range */
262 #define CFG_VMEEAR_BASE 0x60000000
263 #define CFG_VMEEAR_SIZE 0x01000000
265 /* CS8: VME Standard Access Range */
266 #define CFG_VMESAR_BASE 0xFE000000
267 #define CFG_VMESAR_SIZE 0x01000000
269 /* CS9: VME Short I/O Access Range */
270 #define CFG_VMESIOAR_BASE 0xFD000000
271 #define CFG_VMESIOAR_SIZE 0x01000000
273 /*-----------------------------------------------------------------------
274 * Hard Reset Configuration Words
276 * if you change bits in the HRCW, you must also change the CFG_*
277 * defines for the various registers affected by the HRCW e.g. changing
278 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
280 #if defined(CONFIG_BOOT_ROM)
281 #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
282 HRCW_BPS01 | HRCW_CS10PC01)
284 #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
287 /* no slaves so just fill with zeros */
288 #define CFG_HRCW_SLAVE1 0
289 #define CFG_HRCW_SLAVE2 0
290 #define CFG_HRCW_SLAVE3 0
291 #define CFG_HRCW_SLAVE4 0
292 #define CFG_HRCW_SLAVE5 0
293 #define CFG_HRCW_SLAVE6 0
294 #define CFG_HRCW_SLAVE7 0
296 /*-----------------------------------------------------------------------
297 * Internal Memory Mapped Register
299 #define CFG_IMMR 0xF0000000
301 /*-----------------------------------------------------------------------
302 * Definitions for initial stack pointer and data area (in DPRAM)
304 #define CFG_INIT_RAM_ADDR CFG_IMMR
305 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
306 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
307 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
308 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
310 /*-----------------------------------------------------------------------
311 * Start addresses for the final memory configuration
312 * (Set up by the startup code)
313 * Please note that CFG_SDRAM_BASE _must_ start at 0
315 * 60x SDRAM is mapped at CFG_SDRAM_BASE.
317 #define CFG_SDRAM_BASE 0x00000000
318 #define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
319 #define CFG_MONITOR_BASE TEXT_BASE
320 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
321 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
323 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
328 #define CONFIG_PCI_PNP
329 #define CONFIG_EEPRO100
330 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
334 /* environment is in Flash */
335 #define CFG_ENV_IS_IN_FLASH 1
336 #ifdef CONFIG_BOOT_ROM
337 # define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000)
338 # define CFG_ENV_SIZE 0x10000
339 # define CFG_ENV_SECT_SIZE 0x10000
342 /* environment is in EEPROM */
343 #define CFG_ENV_IS_IN_EEPROM 1
344 #define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */
345 #define CFG_I2C_EEPROM_ADDR_LEN 1
346 /* mask of address bits that overflow into the "EEPROM chip address" */
347 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
348 #define CFG_EEPROM_PAGE_WRITE_BITS 4
349 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
350 #define CFG_ENV_OFFSET 512
351 #define CFG_ENV_SIZE (2048 - 512)
355 * Internal Definitions
359 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
360 #define BOOTFLAG_WARM 0x02 /* Software reboot */
363 /*-----------------------------------------------------------------------
364 * Cache Configuration
366 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
367 #if defined(CONFIG_CMD_KGDB)
368 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
371 /*-----------------------------------------------------------------------
372 * HIDx - Hardware Implementation-dependent Registers 2-11
373 *-----------------------------------------------------------------------
374 * HID0 also contains cache control - initially enable both caches and
375 * invalidate contents, then the final state leaves only the instruction
376 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
377 * but Soft reset does not.
379 * HID1 has only read-only information - nothing to set.
381 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
382 HID0_DCI|HID0_IFEM|HID0_ABE)
383 #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
386 /*-----------------------------------------------------------------------
387 * RMR - Reset Mode Register 5-5
388 *-----------------------------------------------------------------------
389 * turn on Checkstop Reset Enable
391 #define CFG_RMR RMR_CSRE
393 /*-----------------------------------------------------------------------
394 * BCR - Bus Configuration 4-25
395 *-----------------------------------------------------------------------
397 #define BCR_APD01 0x10000000
398 #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
400 /*-----------------------------------------------------------------------
401 * SIUMCR - SIU Module Configuration 4-31
402 *-----------------------------------------------------------------------
404 #define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
405 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
407 /*-----------------------------------------------------------------------
408 * SYPCR - System Protection Control 4-35
409 * SYPCR can only be written once after reset!
410 *-----------------------------------------------------------------------
411 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
413 #if defined(CONFIG_WATCHDOG)
414 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
415 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
417 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
418 SYPCR_SWRI|SYPCR_SWP)
419 #endif /* CONFIG_WATCHDOG */
421 /*-----------------------------------------------------------------------
422 * TMCNTSC - Time Counter Status and Control 4-40
423 *-----------------------------------------------------------------------
424 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
425 * and enable Time Counter
427 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
429 /*-----------------------------------------------------------------------
430 * PISCR - Periodic Interrupt Status and Control 4-42
431 *-----------------------------------------------------------------------
432 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
435 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
437 /*-----------------------------------------------------------------------
438 * SCCR - System Clock Control 9-8
439 *-----------------------------------------------------------------------
440 * Ensure DFBRG is Divide by 16
442 #define CFG_SCCR SCCR_DFBRG01
444 /*-----------------------------------------------------------------------
445 * RCCR - RISC Controller Configuration 13-7
446 *-----------------------------------------------------------------------
450 #define CFG_MIN_AM_MASK 0xC0000000
453 * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
454 * refresh rate = 7.68 uS (100 MHz Bus Clock)
457 /*-----------------------------------------------------------------------
458 * MPTPR - Memory Refresh Timer Prescaler Register 10-18
459 *-----------------------------------------------------------------------
461 #define CFG_MPTPR 0x2000
463 /*-----------------------------------------------------------------------
464 * PSRT - Refresh Timer Register 10-16
465 *-----------------------------------------------------------------------
467 #define CFG_PSRT 0x16
469 /*-----------------------------------------------------------------------
470 * PSRT - SDRAM Mode Register 10-10
471 *-----------------------------------------------------------------------
474 /* SDRAM initialization values for 8-column chips
476 #define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
478 ORxS_ROWST_PBI0_A9 |\
481 #define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
482 PSDMR_BSMA_A14_A16 |\
483 PSDMR_SDA10_PBI0_A10 |\
491 /* SDRAM initialization values for 9-column chips
493 #define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
495 ORxS_ROWST_PBI0_A7 |\
498 #define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
499 PSDMR_BSMA_A13_A15 |\
500 PSDMR_SDA10_PBI0_A9 |\
508 /* SDRAM initialization values for 10-column chips
510 #define CFG_OR2_10COL (CFG_MIN_AM_MASK |\
512 ORxS_ROWST_PBI1_A4 |\
515 #define CFG_PSDMR_10COL (PSDMR_PBI |\
516 PSDMR_SDAM_A17_IS_A5 |\
517 PSDMR_BSMA_A13_A15 |\
518 PSDMR_SDA10_PBI1_A6 |\
527 * Init Memory Controller:
529 * Bank Bus Machine PortSz Device
530 * ---- --- ------- ------ ------
531 * 0 60x GPCM 8 bit Boot ROM
532 * 1 60x GPCM 64 bit FLASH
533 * 2 60x SDRAM 64 bit SDRAM
537 #define CFG_MRS_OFFS 0x00000000
539 #ifdef CONFIG_BOOT_ROM
542 #define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
547 #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
555 #define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
560 #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
566 #else /* CONFIG_BOOT_ROM */
569 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
574 #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
582 #define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
587 #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
593 #endif /* CONFIG_BOOT_ROM */
596 /* Bank 2 - 60x bus SDRAM
599 #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
604 #define CFG_OR2_PRELIM CFG_OR2_8COL
606 #define CFG_PSDMR CFG_PSDMR_8COL
607 #endif /* CFG_RAMBOOT */
609 /* Bank 3 - Dual Ported SRAM
611 #define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
616 #define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\
622 /* Bank 4 - DiskOnChip
624 #define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\
629 #define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\
635 /* Bank 5 - FDC37C78 controller
637 #define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
642 #define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\
647 /* Bank 6 - Board control registers
649 #define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\
654 #define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\
658 /* Bank 7 - VME Extended Access Range
660 #define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
665 #define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\
671 /* Bank 8 - VME Standard Access Range
673 #define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\
678 #define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\
684 /* Bank 9 - VME Short I/O Access Range
686 #define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
691 #define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\
697 #endif /* __CONFIG_H */