3 * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
5 * (C) Copyright 2001, 2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /* ------------------------------------------------------------------------- */
30 * board/config.h - configuration options, board specific
37 * High Level Configuration Options
41 #define CONFIG_MPC824X 1
42 #define CONFIG_MPC8245 1
43 #define CONFIG_HIDDEN_DRAGON 1
45 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
53 #define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
54 #define CONFIG_BAUDRATE 9600
55 #define CONFIG_DRAM_SPEED 100 /* MHz */
61 #define CONFIG_BOOTP_BOOTFILESIZE
62 #define CONFIG_BOOTP_BOOTPATH
63 #define CONFIG_BOOTP_GATEWAY
64 #define CONFIG_BOOTP_HOSTNAME
68 * Command line configuration.
70 #include <config_cmd_default.h>
72 #define CONFIG_CMD_EEPROM
73 #define CONFIG_CMD_ELF
74 #define CONFIG_CMD_I2C
75 #define CONFIG_CMD_NET
76 #define CONFIG_CMD_PCI
77 #define CONFIG_CMD_PING
80 * Miscellaneous configurable options
82 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
83 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
84 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
85 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
86 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
87 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
88 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
89 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
91 /*-----------------------------------------------------------------------
93 *-----------------------------------------------------------------------
95 #define CONFIG_PCI /* include pci support */
98 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
100 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
102 #define PCI_ENET0_IOADDR 0x80000000
103 #define PCI_ENET0_MEMADDR 0x80000000
104 #define PCI_ENET1_IOADDR 0x81000000
105 #define PCI_ENET1_MEMADDR 0x81000000
107 #define CONFIG_RTL8139
109 /* Make sure the ethaddr can be overwritten
110 TODO: Remove this on final product
112 #define CONFIG_ENV_OVERWRITE
114 /*-----------------------------------------------------------------------
115 * Start addresses for the final memory configuration
116 * (Set up by the startup code)
117 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
119 #define CONFIG_SYS_SDRAM_BASE 0x00000000
120 #define CONFIG_SYS_MAX_RAM_SIZE 0x02000000
122 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
124 #if defined (USE_DINK32)
125 #define CONFIG_SYS_MONITOR_LEN 0x00030000
126 #define CONFIG_SYS_MONITOR_BASE 0x00090000
127 #define CONFIG_SYS_RAMBOOT 1
128 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
129 #define CONFIG_SYS_INIT_RAM_END 0x10000
130 #define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
131 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
132 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
134 #undef CONFIG_SYS_RAMBOOT
135 #define CONFIG_SYS_MONITOR_LEN 0x00030000
136 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
138 #define CONFIG_SYS_GBL_DATA_SIZE 128
140 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
141 #define CONFIG_SYS_INIT_RAM_END 0x1000
142 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
146 #define CONFIG_SYS_FLASH_BASE 0xFFE00000
147 #define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* Unity has onboard 1MByte flash */
148 #define CONFIG_ENV_IS_IN_FLASH 1
149 #define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
150 #define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
152 #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
154 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
155 #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
157 #define CONFIG_SYS_EUMB_ADDR 0xFC000000
159 #define CONFIG_SYS_ISA_MEM 0xFD000000
160 #define CONFIG_SYS_ISA_IO 0xFE000000
162 #define CONFIG_SYS_FLASH_RANGE_BASE 0xFFE00000 /* flash memory address range */
163 #define CONFIG_SYS_FLASH_RANGE_SIZE 0x00200000
164 #define FLASH_BASE0_PRELIM 0xFFE00000 /* processor board flash */
167 * select i2c support configuration
169 * Supported configurations are {none, software, hardware} drivers.
170 * If the software driver is chosen, there are some additional
171 * configuration items that the driver uses to drive the port pins.
173 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
174 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
175 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
176 #define CONFIG_SYS_I2C_SLAVE 0x7F
178 #ifdef CONFIG_SOFT_I2C
179 #error "Soft I2C is not configured properly. Please review!"
180 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
181 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
182 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
183 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
184 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
185 else iop->pdat &= ~0x00010000
186 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
187 else iop->pdat &= ~0x00020000
188 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
189 #endif /* CONFIG_SOFT_I2C */
191 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
192 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
193 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
194 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
196 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
197 #define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
199 /*-----------------------------------------------------------------------
200 * Definitions for initial stack pointer and data area (in DPRAM)
204 #define CONFIG_WINBOND_83C553 1 /*has a winbond bridge */
205 #define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
206 #define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
207 #define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
209 #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
210 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
212 /* TODO: Change this to VIA686A */
215 * NS87308 Configuration
217 #define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
219 #define CONFIG_SYS_NS87308_BADDR_10 1
221 #define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \
222 CONFIG_SYS_NS87308_UART2 | \
223 CONFIG_SYS_NS87308_POWRMAN | \
224 CONFIG_SYS_NS87308_RTC_APC )
226 #undef CONFIG_SYS_NS87308_PS2MOD
228 #define CONFIG_SYS_NS87308_CS0_BASE 0x0076
229 #define CONFIG_SYS_NS87308_CS0_CONF 0x30
230 #define CONFIG_SYS_NS87308_CS1_BASE 0x0075
231 #define CONFIG_SYS_NS87308_CS1_CONF 0x30
232 #define CONFIG_SYS_NS87308_CS2_BASE 0x0074
233 #define CONFIG_SYS_NS87308_CS2_CONF 0x30
236 * NS16550 Configuration
238 #define CONFIG_SYS_NS16550
239 #define CONFIG_SYS_NS16550_SERIAL
241 #define CONFIG_SYS_NS16550_REG_SIZE 1
243 #if (CONFIG_CONS_INDEX > 2)
244 #define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000
246 #define CONFIG_SYS_NS16550_CLK 1843200
249 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
250 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
251 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500)
252 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600)
255 * Low Level Configuration Settings
256 * (address mappings, register initial values, etc.)
257 * You should know what you are doing if you make changes here.
260 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
262 #define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
263 #define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
265 #define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */
267 /* the following are for SDRAM only*/
268 #define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
269 #define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
270 #define CONFIG_SYS_RDLAT 4 /* data latency from read command */
271 #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
272 #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
273 #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
274 #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
275 #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
277 #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
280 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
281 #define CONFIG_SYS_EXTROM 1
282 #define CONFIG_SYS_REGDIMM 0
285 /* memory bank settings*/
287 * only bits 20-29 are actually used from these vales to set the
288 * start/end address the upper two bits will be 0, and the lower 20
289 * bits will be set to 0x00000 for a start address, or 0xfffff for an
292 #define CONFIG_SYS_BANK0_START 0x00000000
293 #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
294 #define CONFIG_SYS_BANK0_ENABLE 1
295 #define CONFIG_SYS_BANK1_START 0x3ff00000
296 #define CONFIG_SYS_BANK1_END 0x3fffffff
297 #define CONFIG_SYS_BANK1_ENABLE 0
298 #define CONFIG_SYS_BANK2_START 0x3ff00000
299 #define CONFIG_SYS_BANK2_END 0x3fffffff
300 #define CONFIG_SYS_BANK2_ENABLE 0
301 #define CONFIG_SYS_BANK3_START 0x3ff00000
302 #define CONFIG_SYS_BANK3_END 0x3fffffff
303 #define CONFIG_SYS_BANK3_ENABLE 0
304 #define CONFIG_SYS_BANK4_START 0x00000000
305 #define CONFIG_SYS_BANK4_END 0x00000000
306 #define CONFIG_SYS_BANK4_ENABLE 0
307 #define CONFIG_SYS_BANK5_START 0x00000000
308 #define CONFIG_SYS_BANK5_END 0x00000000
309 #define CONFIG_SYS_BANK5_ENABLE 0
310 #define CONFIG_SYS_BANK6_START 0x00000000
311 #define CONFIG_SYS_BANK6_END 0x00000000
312 #define CONFIG_SYS_BANK6_ENABLE 0
313 #define CONFIG_SYS_BANK7_START 0x00000000
314 #define CONFIG_SYS_BANK7_END 0x00000000
315 #define CONFIG_SYS_BANK7_ENABLE 0
317 * Memory bank enable bitmask, specifying which of the banks defined above
318 are actually present. MSB is for bank #7, LSB is for bank #0.
320 #define CONFIG_SYS_BANK_ENABLE 0x01
322 #define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
323 /* see 8240 book for bit definitions */
324 #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
325 /* currently accessed page in memory */
326 /* see 8240 book for details */
328 /* SDRAM 0 - 256MB */
329 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
330 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
332 /* stack in DCACHE @ 1GB (no backing mem) */
333 #if defined(USE_DINK32)
334 #define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
335 #define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
337 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
338 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
342 #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
343 #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
345 /* Flash, config addrs, etc */
346 #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
347 #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
349 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
350 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
351 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
352 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
353 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
354 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
355 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
356 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
359 * For booting Linux, the board info and command line data
360 * have to be in the first 8 MB of memory, since this is
361 * the maximum mapped by the Linux kernel during initialization.
363 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
364 /*-----------------------------------------------------------------------
367 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
368 #define CONFIG_SYS_MAX_FLASH_SECT 36 /* max number of sectors on one chip */
370 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
371 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
373 /*-----------------------------------------------------------------------
374 * Cache Configuration
376 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
377 #if defined(CONFIG_CMD_KGDB)
378 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
382 * Internal Definitions
386 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
387 #define BOOTFLAG_WARM 0x02 /* Software reboot */
389 /* values according to the manual */
390 #define CONFIG_DRAM_50MHZ 1
391 #define CONFIG_SDRAM_50MHZ
394 #define NR_8259_INTS 1
396 #define CONFIG_DISK_SPINUP_TIME 1000000
398 #endif /* __CONFIG_H */