3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
21 #define CONFIG_MPC8272_FAMILY 1
22 #define CONFIG_IDS8247 1
23 #define CPU_ID_STR "MPC8247"
24 #define CONFIG_CPM2 1 /* Has a CPM2 */
26 #define CONFIG_SYS_TEXT_BASE 0xfff00000
28 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
30 #define CONFIG_BOOTCOUNT_LIMIT
32 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
34 #undef CONFIG_BOOTARGS
36 #define CONFIG_EXTRA_ENV_SETTINGS \
38 "nfsargs=setenv bootargs root=/dev/nfs rw " \
39 "nfsroot=${serverip}:${rootpath}\0" \
40 "ramargs=setenv bootargs root=/dev/ram rw " \
41 "console=ttyS0,115200\0" \
42 "addip=setenv bootargs ${bootargs} " \
43 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
44 ":${hostname}:${netdev}:off panic=1\0" \
45 "flash_nfs=run nfsargs addip;" \
46 "bootm ${kernel_addr}\0" \
47 "flash_self=run ramargs addip;" \
48 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
49 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
50 "rootpath=/opt/eldk/ppc_82xx\0" \
51 "bootfile=/tftpboot/IDS8247/uImage\0" \
52 "kernel_addr=ff800000\0" \
53 "ramdisk_addr=ffa00000\0" \
55 #define CONFIG_BOOTCOMMAND "run flash_self"
57 #define CONFIG_MISC_INIT_R 1
59 /* enable I2C and select the hardware/software driver */
60 #define CONFIG_SYS_I2C
61 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
62 #define CONFIG_SYS_I2C_SOFT_SPEED 400000
63 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
65 * Software (bit-bang) I2C driver configuration
68 #define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */
69 #define I2C_ACTIVE (iop->pdir |= 0x00000080)
70 #define I2C_TRISTATE (iop->pdir &= ~0x00000080)
71 #define I2C_READ ((iop->pdat & 0x00000080) != 0)
72 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \
73 else iop->pdat &= ~0x00000080
74 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \
75 else iop->pdat &= ~0x00000100
76 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
79 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
80 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
81 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
82 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
88 * select serial console configuration
89 * use the extern UART for the console
91 #define CONFIG_CONS_INDEX 1
92 #define CONFIG_BAUDRATE 115200
94 * NS16550 Configuration
96 #define CONFIG_SYS_NS16550
97 #define CONFIG_SYS_NS16550_SERIAL
99 #define CONFIG_SYS_NS16550_REG_SIZE 1
101 #define CONFIG_SYS_NS16550_CLK 14745600
103 #define CONFIG_SYS_UART_BASE 0xE0000000
104 #define CONFIG_SYS_UART_SIZE 0x10000
106 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000)
109 /* pass open firmware flat tree */
110 #define CONFIG_OF_LIBFDT 1
111 #define CONFIG_OF_BOARD_SETUP 1
113 #define OF_TBCLK (bd->bi_busfreq / 4)
114 #define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000"
118 * select ethernet configuration
120 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
121 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
124 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
125 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
127 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
128 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
129 #undef CONFIG_ETHER_NONE /* define if ether on something else */
130 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
131 #define CONFIG_ETHER_ON_FCC1
137 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
138 * - Enable Full Duplex in FSMR
140 # define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
141 # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
142 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
143 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
146 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
147 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
149 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
150 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
152 #undef CONFIG_WATCHDOG /* watchdog disabled */
154 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
159 #define CONFIG_BOOTP_SUBNETMASK
160 #define CONFIG_BOOTP_GATEWAY
161 #define CONFIG_BOOTP_HOSTNAME
162 #define CONFIG_BOOTP_BOOTPATH
163 #define CONFIG_BOOTP_BOOTFILESIZE
165 #define CONFIG_RTC_PCF8563
166 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
169 * Command line configuration.
171 #include <config_cmd_default.h>
173 #define CONFIG_CMD_DHCP
174 #define CONFIG_CMD_NFS
175 #define CONFIG_CMD_NAND
176 #define CONFIG_CMD_I2C
177 #define CONFIG_CMD_SNTP
181 * Miscellaneous configurable options
183 #define CONFIG_SYS_LONGHELP /* undef to save memory */
184 #if defined(CONFIG_CMD_KGDB)
185 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
187 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
189 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
190 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
191 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
193 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
194 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
196 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
198 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
200 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
203 * For booting Linux, the board info and command line data
204 * have to be in the first 8 MB of memory, since this is
205 * the maximum mapped by the Linux kernel during initialization.
207 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
209 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
210 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
211 #define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 }
212 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
213 /* What should the base address of the main FLASH be and how big is
214 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk
215 * The main FLASH is whichever is connected to *CS0.
217 #define CONFIG_SYS_FLASH0_BASE 0xFFF00000
218 #define CONFIG_SYS_FLASH0_SIZE 8
220 /* Flash bank size (for preliminary settings)
222 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
224 /*-----------------------------------------------------------------------
227 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
229 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
230 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
232 /* Environment in flash */
233 #define CONFIG_ENV_IS_IN_FLASH 1
234 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000)
235 #define CONFIG_ENV_SIZE 0x20000
236 #define CONFIG_ENV_SECT_SIZE 0x20000
238 /*-----------------------------------------------------------------------
240 *-----------------------------------------------------------------------
242 #if defined(CONFIG_CMD_NAND)
244 #define CONFIG_SYS_NAND0_BASE 0xE1000000
245 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
247 #endif /* CONFIG_CMD_NAND */
249 /*-----------------------------------------------------------------------
250 * Hard Reset Configuration Words
252 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
253 * defines for the various registers affected by the HRCW e.g. changing
254 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
256 #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
258 /* no slaves so just fill with zeros */
259 #define CONFIG_SYS_HRCW_SLAVE1 0
260 #define CONFIG_SYS_HRCW_SLAVE2 0
261 #define CONFIG_SYS_HRCW_SLAVE3 0
262 #define CONFIG_SYS_HRCW_SLAVE4 0
263 #define CONFIG_SYS_HRCW_SLAVE5 0
264 #define CONFIG_SYS_HRCW_SLAVE6 0
265 #define CONFIG_SYS_HRCW_SLAVE7 0
267 /*-----------------------------------------------------------------------
268 * Internal Memory Mapped Register
270 #define CONFIG_SYS_IMMR 0xF0000000
272 /*-----------------------------------------------------------------------
273 * Definitions for initial stack pointer and data area (in DPRAM)
275 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
276 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
277 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
278 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
280 /*-----------------------------------------------------------------------
281 * Start addresses for the final memory configuration
282 * (Set up by the startup code)
283 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
285 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
287 #define CONFIG_SYS_SDRAM_BASE 0x00000000
288 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
289 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
290 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
291 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
293 /*-----------------------------------------------------------------------
294 * Cache Configuration
296 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
297 #if defined(CONFIG_CMD_KGDB)
298 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
301 /*-----------------------------------------------------------------------
302 * HIDx - Hardware Implementation-dependent Registers 2-11
303 *-----------------------------------------------------------------------
304 * HID0 also contains cache control - initially enable both caches and
305 * invalidate contents, then the final state leaves only the instruction
306 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
307 * but Soft reset does not.
309 * HID1 has only read-only information - nothing to set.
312 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
313 #define CONFIG_SYS_HID0_FINAL 0
314 #define CONFIG_SYS_HID2 0
316 /*-----------------------------------------------------------------------
317 * RMR - Reset Mode Register 5-5
318 *-----------------------------------------------------------------------
319 * turn on Checkstop Reset Enable
321 #define CONFIG_SYS_RMR 0
323 /*-----------------------------------------------------------------------
324 * BCR - Bus Configuration 4-25
325 *-----------------------------------------------------------------------
327 #define CONFIG_SYS_BCR 0
329 /*-----------------------------------------------------------------------
330 * SIUMCR - SIU Module Configuration 4-31
331 *-----------------------------------------------------------------------
333 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
335 /*-----------------------------------------------------------------------
336 * SYPCR - System Protection Control 4-35
337 * SYPCR can only be written once after reset!
338 *-----------------------------------------------------------------------
339 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
341 #if defined(CONFIG_WATCHDOG)
342 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
343 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
345 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
346 SYPCR_SWRI|SYPCR_SWP)
347 #endif /* CONFIG_WATCHDOG */
349 /*-----------------------------------------------------------------------
350 * TMCNTSC - Time Counter Status and Control 4-40
351 *-----------------------------------------------------------------------
352 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
353 * and enable Time Counter
355 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
357 /*-----------------------------------------------------------------------
358 * PISCR - Periodic Interrupt Status and Control 4-42
359 *-----------------------------------------------------------------------
360 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
363 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
365 /*-----------------------------------------------------------------------
366 * SCCR - System Clock Control 9-8
367 *-----------------------------------------------------------------------
368 * Ensure DFBRG is Divide by 16
370 #define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01)
372 /*-----------------------------------------------------------------------
373 * RCCR - RISC Controller Configuration 13-7
374 *-----------------------------------------------------------------------
376 #define CONFIG_SYS_RCCR 0
379 * Init Memory Controller:
381 * Bank Bus Machine PortSz Device
382 * ---- --- ------- ------ ------
383 * 0 60x GPCM 16 bit FLASH
384 * 1 60x GPCM 8 bit NAND
385 * 2 60x SDRAM 32 bit SDRAM
386 * 3 60x GPCM 8 bit UART
390 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
392 /* Minimum mask to separate preliminary
393 * address ranges for CS[0:2]
395 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */
397 #define CONFIG_SYS_MPTPR 0x6600
399 /*-----------------------------------------------------------------------------
400 * Address for Mode Register Set (MRS) command
401 *-----------------------------------------------------------------------------
403 #define CONFIG_SYS_MRS_OFFS 0x00000110
408 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
413 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
416 #if defined(CONFIG_CMD_NAND)
417 /* Bank 1 - NAND Flash
419 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE
420 #define CONFIG_SYS_NAND_SIZE 0x8000
422 #define CONFIG_SYS_OR_TIMING_NAND 0x000036
424 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
425 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
428 /* Bank 2 - 60x bus SDRAM
430 #define CONFIG_SYS_PSRT 0x20
431 #define CONFIG_SYS_LSRT 0x20
433 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
438 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2
441 /* SDRAM initialization values
443 #define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
445 ORxS_ROWST_PBI0_A9 |\
448 #define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
449 PSDMR_BSMA_A15_A17 |\
450 PSDMR_SDA10_PBI0_A10 |\
462 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
463 #define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
465 #endif /* __CONFIG_H */