2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
6 * SPDX-License-Identifier: GPL-2.0+
10 * board/config.h - configuration options, board specific
11 * Derived from ../tqm8xx/tqm8xx.c
18 * High Level Configuration Options
22 #define CONFIG_MPC859T 1 /* This is a MPC859T CPU */
23 #define CONFIG_KUP4X 1 /* ...on a KUP4X module */
25 #define CONFIG_SYS_TEXT_BASE 0x40000000
27 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
28 #undef CONFIG_8xx_CONS_SMC2
29 #undef CONFIG_8xx_CONS_NONE
30 #define CONFIG_BAUDRATE 115200 /* console baudrate */
32 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
34 #define CONFIG_BOARD_TYPES 1 /* support board types */
36 #define CONFIG_SYS_8XX_FACT 8 /* Multiply by 8 */
37 #define CONFIG_SYS_8XX_XIN 16000000 /* 16 MHz in */
40 #define MPC8XX_HZ ((CONFIG_SYS_8XX_XIN) * (CONFIG_SYS_8XX_FACT))
42 /* should ALWAYS define this, measure_gclk in speed.c is unreliable */
43 /* in general, we always know this for FADS+new ADS anyway */
44 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
47 #undef CONFIG_BOOTARGS
50 #define CONFIG_EXTRA_ENV_SETTINGS \
51 "slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
52 "run addhw;diskboot 200000 0:1;bootm 200000\0" \
53 "usb_boot=setenv bootargs root=/dev/sda2 ip=off; \
54 run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1; \
55 usb stop; bootm 200000\0" \
56 "nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \
57 "panic_boot=echo No Bootdevice !!! reset\0" \
58 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
59 "ramargs=setenv bootargs root=/dev/ram rw\0" \
60 "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \
61 ":${netmask}:${hostname}:${netdev}:off\0" \
62 "addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \
65 "load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \
66 "update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};" \
67 "cp.b 200000 40040000 14000\0"
69 #define CONFIG_BOOTCOMMAND \
70 "run usb_boot;run slot_a_boot;run nfs_boot;run panic_boot"
73 #define CONFIG_MISC_INIT_R 1
74 #define CONFIG_MISC_INIT_F 1
76 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
77 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
79 #define CONFIG_WATCHDOG 1 /* watchdog enabled */
81 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
83 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
88 #define CONFIG_BOOTP_SUBNETMASK
89 #define CONFIG_BOOTP_GATEWAY
90 #define CONFIG_BOOTP_HOSTNAME
91 #define CONFIG_BOOTP_BOOTPATH
92 #define CONFIG_BOOTP_BOOTFILESIZE
95 #define CONFIG_MAC_PARTITION
96 #define CONFIG_DOS_PARTITION
99 * enable I2C and select the hardware/software driver
101 #define CONFIG_SYS_I2C
102 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
104 #ifdef CONFIG_SYS_I2C_SOFT
105 #define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
106 #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
109 * Software (bit-bang) I2C driver configuration
111 #define PB_SCL 0x00000020 /* PB 26 */
112 #define PB_SDA 0x00000010 /* PB 27 */
114 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
115 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
116 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
117 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
118 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
119 else immr->im_cpm.cp_pbdat &= ~PB_SDA
120 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
121 else immr->im_cpm.cp_pbdat &= ~PB_SCL
122 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
123 #endif /* CONFIG_SYS_I2C_SOFT */
126 /*-----------------------------------------------------------------------
130 #define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
131 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
134 /* List of I2C addresses to be verified by POST */
136 #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
137 CONFIG_SYS_I2C_RTC_ADDR, \
141 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
143 #define CONFIG_SYS_DISCOVER_PHY
146 #undef CONFIG_KUP4K_LOGO
148 /* Define to allow the user to overwrite serial and ethaddr */
149 #define CONFIG_ENV_OVERWRITE
153 #define CONFIG_POST (CONFIG_SYS_POST_CPU | \
154 CONFIG_SYS_POST_RTC | \
159 * Command line configuration.
161 #include <config_cmd_default.h>
163 #define CONFIG_CMD_DATE
164 #define CONFIG_CMD_DHCP
165 #define CONFIG_CMD_FAT
166 #define CONFIG_CMD_I2C
167 #define CONFIG_CMD_IDE
168 #define CONFIG_CMD_NFS
169 #define CONFIG_CMD_SNTP
170 #define CONFIG_CMD_USB
173 #define CONFIG_CMD_DIAG
177 * Miscellaneous configurable options
179 #define CONFIG_SYS_LONGHELP /* undef to save memory */
180 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
181 #if defined(CONFIG_CMD_KGDB)
182 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
184 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
186 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
187 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
188 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
190 #define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */
191 #define CONFIG_SYS_MEMTEST_END 0x003C00000 /* 4 ... 60 MB in DRAM */
192 #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
194 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
196 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
198 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1
201 * Low Level Configuration Settings
202 * (address mappings, register initial values, etc.)
203 * You should know what you are doing if you make changes here.
205 /*-----------------------------------------------------------------------
206 * Internal Memory Mapped Register
208 #define CONFIG_SYS_IMMR 0xFFF00000
210 /*-----------------------------------------------------------------------
211 * Definitions for initial stack pointer and data area (in DPRAM)
213 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
214 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
215 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
216 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
218 /*-----------------------------------------------------------------------
219 * Start addresses for the final memory configuration
220 * (Set up by the startup code)
221 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
223 #define CONFIG_SYS_SDRAM_BASE 0x00000000
224 #define CONFIG_SYS_FLASH_BASE 0x40000000
225 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 256 kB for Monitor */
226 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
227 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
230 * For booting Linux, the board info and command line data
231 * have to be in the first 8 MB of memory, since this is
232 * the maximum mapped by the Linux kernel during initialization.
234 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
236 /*-----------------------------------------------------------------------
239 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
240 #define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
242 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
243 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
245 #define CONFIG_ENV_IS_IN_FLASH 1
246 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
247 #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
248 #define CONFIG_ENV_SECT_SIZE 0x10000
250 /* Address and size of Redundant Environment Sector */
252 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
253 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
255 /*-----------------------------------------------------------------------
256 * Hardware Information Block
259 #define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
260 #define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */
261 #define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
263 /*-----------------------------------------------------------------------
264 * Cache Configuration
266 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
267 #if defined(CONFIG_CMD_KGDB)
268 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
271 /*-----------------------------------------------------------------------
272 * SYPCR - System Protection Control 11-9
273 * SYPCR can only be written once after reset!
274 *-----------------------------------------------------------------------
275 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
277 #if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */
278 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
279 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
281 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
284 /*-----------------------------------------------------------------------
285 * SIUMCR - SIU Module Configuration 11-6
286 *-----------------------------------------------------------------------
287 * PCMCIA config., multi-function pin tri-state
289 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
291 /*-----------------------------------------------------------------------
292 * TBSCR - Time Base Status and Control 11-26
293 *-----------------------------------------------------------------------
294 * Clear Reference Interrupt Status, Timebase freezing enabled
296 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
299 /*-----------------------------------------------------------------------
300 * PISCR - Periodic Interrupt Status and Control 11-31
301 *-----------------------------------------------------------------------
302 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
304 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
307 /*-----------------------------------------------------------------------
308 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
309 *-----------------------------------------------------------------------
310 * set the PLL, the low-power modes and the reset control (15-29)
312 #define CONFIG_SYS_PLPRCR ((CONFIG_SYS_8XX_FACT << PLPRCR_MFI_SHIFT) | \
313 PLPRCR_SPLSS | PLPRCR_TEXPS)
316 /*-----------------------------------------------------------------------
317 * SCCR - System Clock and reset Control Register 15-27
318 *-----------------------------------------------------------------------
319 * Set clock output, timebase and RTC source and divider,
320 * power management and some other internal clocks
322 #define SCCR_MASK SCCR_EBDF00
323 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | \
324 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
325 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
328 /*-----------------------------------------------------------------------
330 *-----------------------------------------------------------------------
334 /* KUP4K use both slots, SLOT_A as "primary". */
335 #define CONFIG_PCMCIA_SLOT_A 1
337 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
338 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
339 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
340 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
341 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
342 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
343 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
344 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
346 #define PCMCIA_SOCKETS_NO 1
347 #define PCMCIA_MEM_WIN_NO 8
348 /*-----------------------------------------------------------------------
349 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
350 *-----------------------------------------------------------------------
353 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
354 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
356 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
357 #define CONFIG_IDE_LED 1 /* LED for ide supported */
358 #undef CONFIG_IDE_RESET /* reset for ide not supported */
360 #define CONFIG_SYS_IDE_MAXBUS 1
361 #define CONFIG_SYS_IDE_MAXDEVICE 2
363 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
365 #define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
367 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
369 /* Offset for data I/O */
370 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
372 /* Offset for normal register accesses */
373 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
375 /* Offset for alternate registers */
376 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
379 /*-----------------------------------------------------------------------
381 *-----------------------------------------------------------------------
384 #define CONFIG_SYS_DER 0
387 * Init Memory Controller:
389 * BR0/1 and OR0/1 (FLASH)
391 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
393 /* used to re-map FLASH both when starting from SRAM or FLASH:
394 * restrict access enough to keep SRAM working (if any)
395 * but not too much to meddle with FLASH accesses
397 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
398 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
403 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
404 OR_SCY_2_CLK | OR_EHTR | OR_BI)
406 #define CONFIG_SYS_OR0_REMAP \
407 (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
408 #define CONFIG_SYS_OR0_PRELIM \
409 (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
410 #define CONFIG_SYS_BR0_PRELIM \
411 ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
414 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
415 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
418 #define CONFIG_SYS_MPTPR 0x400
421 * MAMR settings for SDRAM
423 #define CONFIG_SYS_MAMR 0x80802114
430 #define CONFIG_SYS_OR4 0xFFFF8926
431 #define CONFIG_SYS_BR4 0x90000401
433 #define LATCH_ADDR 0x90000200
435 #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
437 #define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
438 #define CONFIG_SILENT_CONSOLE 1
440 #define CONFIG_USB_STORAGE 1
441 #define CONFIG_USB_SL811HS 1
443 #endif /* __CONFIG_H */