2 * Configuation settings for the Freescale MCF54418 TWR board.
4 * Copyright 2010-2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
21 #define CONFIG_MCF5441x /* define processor family */
22 #define CONFIG_M54418 /* define processor type */
23 #define CONFIG_M54418TWR /* M54418TWR board */
25 #define CONFIG_MCFUART
26 #define CONFIG_SYS_UART_PORT (0)
27 #define CONFIG_BAUDRATE 115200
28 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
30 #undef CONFIG_WATCHDOG
32 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
37 #define CONFIG_BOOTP_BOOTFILESIZE
38 #define CONFIG_BOOTP_BOOTPATH
39 #define CONFIG_BOOTP_GATEWAY
40 #define CONFIG_BOOTP_HOSTNAME
42 /* Command line configuration */
43 #include <config_cmd_default.h>
45 #define CONFIG_CMD_BOOTD
46 #define CONFIG_CMD_CACHE
47 #undef CONFIG_CMD_DATE
48 #define CONFIG_CMD_DHCP
49 #define CONFIG_CMD_ELF
50 #undef CONFIG_CMD_FLASH
52 #undef CONFIG_CMD_JFFS2
54 #define CONFIG_CMD_MEMORY
55 #define CONFIG_CMD_MISC
56 #define CONFIG_CMD_MII
57 #undef CONFIG_CMD_NAND
58 #undef CONFIG_CMD_NAND_YAFFS
59 #define CONFIG_CMD_NET
60 #define CONFIG_CMD_NFS
61 #define CONFIG_CMD_PING
62 #define CONFIG_CMD_REGINFO
63 #define CONFIG_CMD_SPI
65 #undef CONFIG_CMD_IMLS
67 #undef CONFIG_CMD_LOADB
68 #undef CONFIG_CMD_LOADS
73 #ifdef CONFIG_CMD_NAND
74 #define CONFIG_JFFS2_NAND
75 #define CONFIG_NAND_FSL_NFC
76 #define CONFIG_SYS_NAND_BASE 0xFC0FC000
77 #define CONFIG_SYS_MAX_NAND_DEVICE 1
78 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
79 #define CONFIG_SYS_NAND_SELECT_DEVICE
80 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
83 /* Network configuration */
86 #define CONFIG_NET_MULTI 1
88 #define CONFIG_MII_INIT 1
89 #define CONFIG_SYS_DISCOVER_PHY
90 #define CONFIG_SYS_RX_ETH_BUFFER 2
91 #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
92 #define CONFIG_SYS_TX_ETH_BUFFER 2
93 #define CONFIG_HAS_ETH1
95 #define CONFIG_SYS_FEC0_PINMUX 0
96 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
97 #define CONFIG_SYS_FEC1_PINMUX 0
98 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
99 #define MCFFEC_TOUT_LOOP 50000
100 #define CONFIG_SYS_FEC0_PHYADDR 0
101 #define CONFIG_SYS_FEC1_PHYADDR 1
103 #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
105 #ifdef CONFIG_SYS_NAND_BOOT
106 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \
107 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
108 "-(jffs2) console=ttyS0,115200"
110 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \
111 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \
112 __stringify(CONFIG_IPADDR) " ip=" \
113 __stringify(CONFIG_IPADDR) ":" \
114 __stringify(CONFIG_SERVERIP)":" \
115 __stringify(CONFIG_GATEWAYIP)": " \
116 __stringify(CONFIG_NETMASK) \
117 "::eth0:off:rw console=ttyS0,115200"
120 #define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
121 #define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
122 #define CONFIG_ETHPRIME "FEC0"
123 #define CONFIG_IPADDR 192.168.1.2
124 #define CONFIG_NETMASK 255.255.255.0
125 #define CONFIG_SERVERIP 192.168.1.1
126 #define CONFIG_GATEWAYIP 192.168.1.1
128 #define CONFIG_OVERWRITE_ETHADDR_ONCE
129 #define CONFIG_SYS_FEC_BUF_USE_SRAM
130 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
131 #ifndef CONFIG_SYS_DISCOVER_PHY
132 #define FECDUPLEX FULL
133 #define FECSPEED _100BASET
137 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
138 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
140 #endif /* CONFIG_SYS_DISCOVER_PHY */
143 #define CONFIG_HOSTNAME M54418TWR
145 #if defined(CONFIG_CF_SBF)
146 /* ST Micro serial flash */
147 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
148 #define CONFIG_EXTRA_ENV_SETTINGS \
150 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
151 "loadaddr=0x40010000\0" \
152 "sbfhdr=sbfhdr.bin\0" \
153 "uboot=u-boot.bin\0" \
154 "load=tftp ${loadaddr} ${sbfhdr};" \
155 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
156 "upd=run load; run prog\0" \
157 "prog=sf probe 0:1 1000000 3;" \
158 "sf erase 0 40000;" \
159 "sf write ${loadaddr} 0 40000;" \
162 #elif defined(CONFIG_SYS_NAND_BOOT)
163 #define CONFIG_EXTRA_ENV_SETTINGS \
165 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
166 "loadaddr=0x40010000\0" \
167 "u-boot=u-boot.bin\0" \
168 "load=tftp ${loadaddr} ${u-boot};\0" \
169 "upd=run load; run prog\0" \
170 "prog=nand device 0;" \
171 "nand erase 0 40000;" \
172 "nb_update ${loadaddr} ${filesize};" \
176 #define CONFIG_SYS_UBOOT_END 0x3FFFF
177 #define CONFIG_EXTRA_ENV_SETTINGS \
179 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
180 "loadaddr=40010000\0" \
181 "u-boot=u-boot.bin\0" \
182 "load=tftp ${loadaddr) ${u-boot}\0" \
183 "upd=run load; run prog\0" \
184 "prog=prot off mram" " ;" \
185 "cp.b ${loadaddr} 0 ${filesize};" \
192 #define CONFIG_RTC_MCFRRTC
193 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
196 #define CONFIG_MCFTMR
200 #undef CONFIG_SYS_FSL_I2C
201 #undef CONFIG_HARD_I2C /* I2C with hardware support */
202 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
203 /* I2C speed and slave address */
204 #define CONFIG_SYS_I2C_SPEED 80000
205 #define CONFIG_SYS_I2C_SLAVE 0x7F
206 #define CONFIG_SYS_I2C_OFFSET 0x58000
207 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
209 /* DSPI and Serial Flash */
210 #define CONFIG_CF_SPI
211 #define CONFIG_CF_DSPI
212 #define CONFIG_SERIAL_FLASH
213 #define CONFIG_HARD_SPI
214 #define CONFIG_SYS_SBFHDR_SIZE 0x7
215 #ifdef CONFIG_CMD_SPI
216 # define CONFIG_SPI_FLASH
217 # define CONFIG_SPI_FLASH_ATMEL
219 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
220 DSPI_CTAR_PCSSCK_1CLK | \
221 DSPI_CTAR_PASC(0) | \
223 DSPI_CTAR_CSSCK(0) | \
226 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
227 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
230 /* Input, PCI, Flexbus, and VCO */
231 #define CONFIG_EXTRA_CLOCK
233 #define CONFIG_PRAM 2048 /* 2048 KB */
236 #define CONFIG_SYS_HUSH_PARSER 1
237 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
239 #define CONFIG_SYS_PROMPT "-> "
240 #define CONFIG_SYS_LONGHELP /* undef to save memory */
242 #if defined(CONFIG_CMD_KGDB)
243 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
245 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
247 /* Print Buffer Size */
248 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
249 sizeof(CONFIG_SYS_PROMPT) + 16)
250 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
251 /* Boot Argument Buffer Size */
252 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
254 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
256 #define CONFIG_SYS_HZ 1000
258 #define CONFIG_SYS_MBAR 0xFC000000
261 * Low Level Configuration Settings
262 * (address mappings, register initial values, etc.)
263 * You should know what you are doing if you make changes here.
266 /*-----------------------------------------------------------------------
267 * Definitions for initial stack pointer and data area (in DPRAM)
269 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
270 /* End of used area in internal SRAM */
271 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
272 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
273 /* size in bytes reserved for initial data */
274 #define CONFIG_SYS_GBL_DATA_SIZE 256
275 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
276 CONFIG_SYS_GBL_DATA_SIZE) - 32)
277 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
278 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
280 /*-----------------------------------------------------------------------
281 * Start addresses for the final memory configuration
282 * (Set up by the startup code)
283 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
285 #define CONFIG_SYS_SDRAM_BASE 0x40000000
286 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
288 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
289 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
290 #define CONFIG_SYS_DRAM_TEST
292 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
293 #define CONFIG_SERIAL_BOOT
296 #if defined(CONFIG_SERIAL_BOOT)
297 #define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
299 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
302 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
303 /* Reserve 256 kB for Monitor */
304 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
305 /* Reserve 256 kB for malloc() */
306 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
309 * For booting Linux, the board info and command line data
310 * have to be in the first 8 MB of memory, since this is
311 * the maximum mapped by the Linux kernel during initialization ??
313 /* Initial Memory map for Linux */
314 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
315 (CONFIG_SYS_SDRAM_SIZE << 20))
317 /* Configuration for environment
318 * Environment is embedded in u-boot in the second sector of the flash
320 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
321 #define CONFIG_SYS_NO_FLASH
322 #define CONFIG_ENV_IS_IN_MRAM 1
323 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
324 #define CONFIG_ENV_SIZE 0x1000
327 #if defined(CONFIG_CF_SBF)
328 #define CONFIG_SYS_NO_FLASH
329 #define CONFIG_ENV_IS_IN_SPI_FLASH 1
330 #define CONFIG_ENV_SPI_CS 1
331 #define CONFIG_ENV_OFFSET 0x40000
332 #define CONFIG_ENV_SIZE 0x2000
333 #define CONFIG_ENV_SECT_SIZE 0x10000
335 #if defined(CONFIG_SYS_NAND_BOOT)
336 #define CONFIG_SYS_NO_FLASH
337 #define CONFIG_ENV_IS_NOWHERE
338 #define CONFIG_ENV_OFFSET 0x80000
339 #define CONFIG_ENV_SIZE 0x20000
340 #define CONFIG_ENV_SECT_SIZE 0x20000
342 #undef CONFIG_ENV_OVERWRITE
344 /* FLASH organization */
345 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
347 #undef CONFIG_SYS_FLASH_CFI
348 #ifdef CONFIG_SYS_FLASH_CFI
350 #define CONFIG_FLASH_CFI_DRIVER 1
351 /* Max size that the board might have */
352 #define CONFIG_SYS_FLASH_SIZE 0x1000000
353 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
354 /* max number of memory banks */
355 #define CONFIG_SYS_MAX_FLASH_BANKS 1
356 /* max number of sectors on one chip */
357 #define CONFIG_SYS_MAX_FLASH_SECT 270
358 /* "Real" (hardware) sectors protection */
359 #define CONFIG_SYS_FLASH_PROTECTION
360 #define CONFIG_SYS_FLASH_CHECKSUM
361 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
363 /* max number of sectors on one chip */
364 #define CONFIG_SYS_MAX_FLASH_SECT 270
365 /* max number of sectors on one chip */
366 #define CONFIG_SYS_MAX_FLASH_BANKS 0
370 * This is setting for JFFS2 support in u-boot.
371 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
373 #ifdef CONFIG_CMD_JFFS2
374 #define CONFIG_JFFS2_DEV "nand0"
375 #define CONFIG_JFFS2_PART_OFFSET (0x800000)
376 #define CONFIG_CMD_MTDPARTS
377 #define CONFIG_MTD_DEVICE
378 #define MTDIDS_DEFAULT "nand0=m54418twr.nand"
380 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \
386 #ifdef CONFIG_CMD_UBI
387 #define CONFIG_CMD_MTDPARTS
388 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */
389 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
390 #define CONFIG_RBTREE
391 #define MTDIDS_DEFAULT "nand0=NAND"
392 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \
395 /* Cache Configuration */
396 #define CONFIG_SYS_CACHELINE_SIZE 16
397 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
398 CONFIG_SYS_INIT_RAM_SIZE - 8)
399 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
400 CONFIG_SYS_INIT_RAM_SIZE - 4)
401 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
402 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
403 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
404 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
405 CF_ACR_EN | CF_ACR_SM_ALL)
406 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
407 CF_CACR_ICINVA | CF_CACR_EUSP)
408 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
409 CF_CACR_DEC | CF_CACR_DDCM_P | \
410 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
412 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
413 CONFIG_SYS_INIT_RAM_SIZE - 12)
415 /*-----------------------------------------------------------------------
416 * Memory bank definitions
419 * CS0 - NOR Flash 16MB
428 #define CONFIG_SYS_CS0_BASE 0x00000000
429 #define CONFIG_SYS_CS0_MASK 0x000F0101
430 #define CONFIG_SYS_CS0_CTRL 0x00001D60
432 #endif /* _M54418TWR_H */