2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 /***********************************************************
32 * High Level Configuration Options
34 ***********************************************************/
35 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
36 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
37 #define CONFIG_MIP405 1 /* ...on a MIP405 board */
39 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
41 /***********************************************************
42 * Note that it may also be a MIP405T board which is a subset of the
44 ***********************************************************/
45 /***********************************************************
47 * CONFIG_BOOT_PCI is only used for first boot-up and should
48 * NOT be enabled for production bootloader
49 ***********************************************************/
50 /*#define CONFIG_BOOT_PCI 1*/
51 /***********************************************************
53 ***********************************************************/
54 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
60 #define CONFIG_BOOTP_BOOTFILESIZE
61 #define CONFIG_BOOTP_BOOTPATH
62 #define CONFIG_BOOTP_GATEWAY
63 #define CONFIG_BOOTP_HOSTNAME
67 * Command line configuration.
69 #include <config_cmd_default.h>
71 #define CONFIG_CMD_CACHE
72 #define CONFIG_CMD_DATE
73 #define CONFIG_CMD_DHCP
74 #define CONFIG_CMD_EEPROM
75 #define CONFIG_CMD_ELF
76 #define CONFIG_CMD_FAT
77 #define CONFIG_CMD_I2C
78 #define CONFIG_CMD_IDE
79 #define CONFIG_CMD_IRQ
80 #define CONFIG_CMD_JFFS2
81 #define CONFIG_CMD_MII
82 #define CONFIG_CMD_PCI
83 #define CONFIG_CMD_PING
84 #define CONFIG_CMD_REGINFO
85 #define CONFIG_CMD_SAVES
86 #define CONFIG_CMD_BSP
88 #if !defined(CONFIG_MIP405T)
89 #define CONFIG_CMD_USB
93 #define CONFIG_SYS_HUSH_PARSER
94 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
95 /**************************************************************
97 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
99 * The Atmel EEPROM uses 16Bit addressing.
100 ***************************************************************/
102 #define CONFIG_HARD_I2C /* I2c with hardware support */
103 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
104 #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
105 #define CONFIG_SYS_I2C_SLAVE 0x7F
107 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
108 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
109 /* mask of address bits that overflow into the "EEPROM chip address" */
110 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
111 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
112 /* 64 byte page write mode using*/
113 /* last 6 bits of the address */
114 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
117 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
118 #define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
119 #define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
121 /***************************************************************
122 * Definitions for Serial Presence Detect EEPROM address
123 * (to get SDRAM settings)
124 ***************************************************************/
125 /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
126 #define SDRAM_EEPROM_READ_ADDRESS 0xA1
128 /**************************************************************
129 * Environment definitions
130 **************************************************************/
131 #define CONFIG_BAUDRATE 9600 /* STD Baudrate */
132 #define CONFIG_BOOTDELAY 5
133 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
134 /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
135 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
137 #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
138 #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
140 #define CONFIG_IPADDR 10.0.0.100
141 #define CONFIG_SERVERIP 10.0.0.1
142 #define CONFIG_PREBOOT
143 /***************************************************************
144 * defines if the console is stored in the environment
145 ***************************************************************/
146 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
147 /***************************************************************
148 * defines if an overwrite_console function exists
149 *************************************************************/
150 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
151 #define CONFIG_SYS_CONSOLE_INFO_QUIET
152 /***************************************************************
153 * defines if the overwrite_console should be stored in the
155 **************************************************************/
156 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
158 /**************************************************************
160 *************************************************************/
161 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
162 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
164 #define CONFIG_MISC_INIT_R
165 /***********************************************************
166 * Miscellaneous configurable options
167 **********************************************************/
168 #define CONFIG_SYS_LONGHELP /* undef to save memory */
169 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
170 #if defined(CONFIG_CMD_KGDB)
171 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
173 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
175 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
176 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
177 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
179 #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
180 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
182 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
183 #define CONFIG_SYS_NS16550
184 #define CONFIG_SYS_NS16550_SERIAL
185 #define CONFIG_SYS_NS16550_REG_SIZE 1
186 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
188 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
189 #define CONFIG_SYS_BASE_BAUD 916667
191 /* The following table includes the supported baudrates */
192 #define CONFIG_SYS_BAUDRATE_TABLE \
193 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
194 57600, 115200, 230400, 460800, 921600 }
196 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
197 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
199 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
201 /*-----------------------------------------------------------------------
203 *-----------------------------------------------------------------------
205 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
206 #define PCI_HOST_FORCE 1 /* configure as pci host */
207 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
209 #define CONFIG_PCI /* include pci support */
210 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
211 #define CONFIG_PCI_PNP /* pci plug-and-play */
212 /* resource configuration */
213 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
214 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
215 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
216 #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
217 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
218 #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
219 #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
220 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
222 /*-----------------------------------------------------------------------
223 * Start addresses for the final memory configuration
224 * (Set up by the startup code)
225 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
227 #define CONFIG_SYS_SDRAM_BASE 0x00000000
228 #define CONFIG_SYS_FLASH_BASE 0xFFF80000
229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
230 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
231 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
234 * For booting Linux, the board info and command line data
235 * have to be in the first 8 MB of memory, since this is
236 * the maximum mapped by the Linux kernel during initialization.
238 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
239 /*-----------------------------------------------------------------------
242 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
243 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
245 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
246 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
252 /* No command line, one static partition, whole device */
253 #undef CONFIG_CMD_MTDPARTS
254 #define CONFIG_JFFS2_DEV "nor0"
255 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
256 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
258 /* mtdparts command line support */
259 /* Note: fake mtd_id used, no linux mtd map file */
261 #define CONFIG_CMD_MTDPARTS
262 #define MTDIDS_DEFAULT "nor0=mip405-0"
263 #define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
266 /*-----------------------------------------------------------------------
267 * Logbuffer Configuration
269 #undef CONFIG_LOGBUFFER /* supported but not enabled */
270 /*-----------------------------------------------------------------------
271 * Bootcountlimit Configuration
273 #undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
275 /*-----------------------------------------------------------------------
278 #if 0 /* enable this if POST is desired (is supported but not enabled) */
279 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
280 CONFIG_SYS_POST_CPU | \
281 CONFIG_SYS_POST_RTC | \
286 * Init Memory Controller:
288 #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
289 #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
290 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
291 #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
293 #define CONFIG_BOARD_EARLY_INIT_F 1
295 /* Peripheral Bus Mapping */
296 #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
297 #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
298 #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
300 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
301 #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
304 /*-----------------------------------------------------------------------
305 * Definitions for initial stack pointer and data area (in On Chip SRAM)
307 #define CONFIG_SYS_TEMP_STACK_OCM 1
308 #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
309 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
310 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
311 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of On Chip SRAM */
312 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
313 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
314 /* reserve some memory for POST and BOOT limit info */
315 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
317 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
318 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
322 * Internal Definitions
326 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
327 #define BOOTFLAG_WARM 0x02 /* Software reboot */
330 /***********************************************************************
331 * External peripheral base address
332 ***********************************************************************/
333 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
335 /***********************************************************************
337 ***********************************************************************/
338 #define CONFIG_LAST_STAGE_INIT
339 /************************************************************
341 ***********************************************************/
342 #define CONFIG_PPC4xx_EMAC
343 #define CONFIG_MII 1 /* MII PHY management */
344 #define CONFIG_PHY_ADDR 1 /* PHY address */
345 #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
346 #define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
347 #define CONFIG_NET_MULTI
348 /************************************************************
350 ***********************************************************/
351 #define CONFIG_RTC_MC146818
352 #undef CONFIG_WATCHDOG /* watchdog disabled */
354 /************************************************************
356 ************************************************************/
357 #if defined(CONFIG_MIP405T)
358 #define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
360 #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
363 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
365 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
366 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
367 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
368 #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
369 #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
370 #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
372 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
373 #undef CONFIG_IDE_LED /* no led for ide supported */
374 #define CONFIG_IDE_RESET /* reset for ide supported... */
375 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
376 #define CONFIG_SUPPORT_VFAT
377 /************************************************************
378 * ATAPI support (experimental)
379 ************************************************************/
380 #define CONFIG_ATAPI /* enable ATAPI Support */
382 /************************************************************
383 * DISK Partition support
384 ************************************************************/
385 #define CONFIG_DOS_PARTITION
386 #define CONFIG_MAC_PARTITION
387 #define CONFIG_ISO_PARTITION /* Experimental */
389 /************************************************************
391 ************************************************************/
392 #undef CONFIG_ISA_KEYBOARD
394 /************************************************************
396 ************************************************************/
397 #define CONFIG_VIDEO /*To enable video controller support */
398 #define CONFIG_VIDEO_CT69000
399 #define CONFIG_CFB_CONSOLE
400 #define CONFIG_VIDEO_LOGO
401 #define CONFIG_CONSOLE_EXTRA_INFO
402 #define CONFIG_VGA_AS_SINGLE_DEVICE
403 #define CONFIG_VIDEO_SW_CURSOR
404 #undef CONFIG_VIDEO_ONBOARD
405 /************************************************************
406 * USB support EXPERIMENTAL
407 ************************************************************/
408 #if !defined(CONFIG_MIP405T)
409 #define CONFIG_USB_UHCI
410 #define CONFIG_USB_KEYBOARD
411 #define CONFIG_USB_STORAGE
413 /* Enable needed helper functions */
414 #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
416 /************************************************************
418 ************************************************************/
419 #if defined(CONFIG_CMD_KGDB)
420 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
421 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
424 /************************************************************
425 * support BZIP2 compression
426 ************************************************************/
427 #define CONFIG_BZIP2 1
429 /************************************************************
431 ************************************************************/
433 #define VERSION_TAG "released"
434 #if !defined(CONFIG_MIP405T)
435 #define CONFIG_ISO_STRING "MEV-10072-001"
437 #define CONFIG_ISO_STRING "MEV-10082-001"
440 #if !defined(CONFIG_BOOT_PCI)
441 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
443 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
447 #endif /* __CONFIG_H */