2 * Copyright 2004 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8349ads board configuration file
26 * Please refer to doc/README.mpc83xxads for more info.
37 * High Level Configuration Options
39 #define CONFIG_E300 1 /* E300 Family */
40 #define CONFIG_MPC83XX 1 /* MPC83XX family */
41 #define CONFIG_MPC8349 1 /* MPC8349 specific */
42 #define CONFIG_MPC8349ADS 1 /* MPC8349ADS board specific */
45 #define CONFIG_TSEC_ENET /* tsec ethernet support */
46 #define CONFIG_ENV_OVERWRITE
48 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
50 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
54 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
56 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
59 #ifndef CONFIG_SYS_CLK_FREQ
61 #define CONFIG_SYS_CLK_FREQ 66000000
63 #define CONFIG_SYS_CLK_FREQ 33000000
67 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
69 #define CFG_IMMRBAR 0xE0000000
71 #undef CFG_DRAM_TEST /* memory test, takes time */
72 #define CFG_MEMTEST_START 0x00000000 /* memtest region */
73 #define CFG_MEMTEST_END 0x00100000
79 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
80 #define CFG_SDRAM_BASE CFG_DDR_BASE
81 #undef CONFIG_DDR_2T_TIMING
82 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
84 #if defined(CONFIG_SPD_EEPROM)
86 * Determine DDR configuration from I2C interface.
88 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
91 * Manually set up DDR parameters
93 #define CFG_DDR_SIZE 256 /* Mb */
94 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
95 #define CFG_DDR_TIMING_1 0x37344321
96 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
97 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
98 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
99 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
103 * SDRAM on the Local Bus
105 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
106 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
109 * FLASH on the Local Bus
111 #define CFG_FLASH_CFI /* use the Common Flash Interface */
112 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
113 #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
114 #define CFG_FLASH_SIZE 8 /* FLASH size in MB */
115 /* #define CFG_FLASH_USE_BUFFER_WRITE */
117 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
118 (2 << BR_PS_SHIFT) | /* 32 bit port size */ \
120 #define CFG_OR0_PRELIM 0xff806ff7 /* 16Mb Flash size*/
121 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
122 #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 16Mb window size */
124 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
125 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */
127 #undef CFG_FLASH_CHECKSUM
128 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
129 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
131 #define CFG_MID_FLASH_JUMP 0x7F000000
132 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
134 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
141 * BCSR register on local bus 32KB, 8-bit wide for ADS config reg
143 #define CFG_BCSR 0xF8000000
144 #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
145 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
146 #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */
147 #define CFG_OR1_PRELIM 0xFFFFE8f0 /* length 32K */
149 #define CONFIG_L1_INIT_RAM
150 #define CFG_INIT_RAM_LOCK 1
151 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
152 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
154 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
155 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
156 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
158 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
159 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
162 * Local Bus LCRR and LBCR regs
163 * LCRR: DLL bypass, Clock divider is 4
164 * External Local Bus rate is
165 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
167 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
168 #define CFG_LBC_LBCR 0x00000000
170 #define CFG_LB_SDRAM /* if board has SRDAM on local bus */
173 /*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/
175 * Base Register 2 and Option Register 2 configure SDRAM.
176 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
179 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
180 * port-size = 32-bits = BR2[19:20] = 11
181 * no parity checking = BR2[21:22] = 00
182 * SDRAM for MSEL = BR2[24:26] = 011
185 * 0 4 8 12 16 20 24 28
186 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
188 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
189 * FIXME: the top 17 bits of BR2.
192 #define CFG_BR2_PRELIM 0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/
193 #define CFG_LBLAWBAR2_PRELIM 0xF0000000
194 #define CFG_LBLAWAR2_PRELIM 0x80000019 /*64M*/
197 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
200 * 64MB mask for AM, OR2[0:7] = 1111 1100
201 * XAM, OR2[17:18] = 11
202 * 9 columns OR2[19-21] = 010
203 * 13 rows OR2[23-25] = 100
204 * EAD set for extra time OR[31] = 1
206 * 0 4 8 12 16 20 24 28
207 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
210 #define CFG_OR2_PRELIM 0xfc006901
212 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
213 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/
218 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
219 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
220 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
221 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
222 #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16))
223 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
224 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
225 #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
226 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
227 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
228 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
229 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
230 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
231 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
232 #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27))
233 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
234 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
235 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
237 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
238 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
239 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
240 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
241 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
242 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
243 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
244 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
246 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \
247 | CFG_LBC_LSDMR_BSMA1516 \
248 | CFG_LBC_LSDMR_RFCR8 \
249 | CFG_LBC_LSDMR_PRETOACT6 \
250 | CFG_LBC_LSDMR_ACTTORW3 \
251 | CFG_LBC_LSDMR_BL8 \
252 | CFG_LBC_LSDMR_WRC3 \
253 | CFG_LBC_LSDMR_CL3 \
257 * SDRAM Controller configuration sequence.
259 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
260 | CFG_LBC_LSDMR_OP_PCHALL)
261 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
262 | CFG_LBC_LSDMR_OP_ARFRSH)
263 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
264 | CFG_LBC_LSDMR_OP_ARFRSH)
265 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
266 | CFG_LBC_LSDMR_OP_MRW)
267 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
268 | CFG_LBC_LSDMR_OP_NORMAL)
274 #define CONFIG_CONS_INDEX 1
275 #undef CONFIG_SERIAL_SOFTWARE_FIFO
277 #define CFG_NS16550_SERIAL
278 #define CFG_NS16550_REG_SIZE 1
279 #define CFG_NS16550_CLK get_bus_freq(0)
281 #define CFG_BAUDRATE_TABLE \
282 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
284 #define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500)
285 #define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600)
287 /* Use the HUSH parser */
288 #define CFG_HUSH_PARSER
289 #ifdef CFG_HUSH_PARSER
290 #define CFG_PROMPT_HUSH_PS2 "> "
294 #define CONFIG_HARD_I2C /* I2C with hardware support*/
295 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
296 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
297 #define CFG_I2C_SLAVE 0x7F
298 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
299 #define CFG_I2C_OFFSET 0x3000
300 #define CFG_I2C2_OFFSET 0x3100
303 #define CFG_TSEC1_OFFSET 0x24000
304 #define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET)
305 #define CFG_TSEC2_OFFSET 0x25000
306 #define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
308 /* IO Configuration */
309 #define CFG_IO_CONF (\
323 * Addresses are mapped 1-1.
325 #define CFG_PCI1_MEM_BASE 0x80000000
326 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
327 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
328 #define CFG_PCI1_IO_BASE 0x00000000
329 #define CFG_PCI1_IO_PHYS 0xe2000000
330 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
332 #define CFG_PCI2_MEM_BASE 0xA0000000
333 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
334 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
335 #define CFG_PCI2_IO_BASE 0x00000000
336 #define CFG_PCI2_IO_PHYS 0xe3000000
337 #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
338 #if defined(CONFIG_PCI)
341 #if defined(PCI_64BIT)
347 #define CONFIG_NET_MULTI
348 #define CONFIG_PCI_PNP /* do pci plug-and-play */
350 #undef CONFIG_EEPRO100
353 #if !defined(CONFIG_PCI_PNP)
354 #define PCI_ENET0_IOADDR 0xFIXME
355 #define PCI_ENET0_MEMADDR 0xFIXME
356 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
359 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
360 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
362 #endif /* CONFIG_PCI */
364 #if defined(CONFIG_TSEC_ENET)
365 #ifndef CONFIG_NET_MULTI
366 #define CONFIG_NET_MULTI 1
369 #define CONFIG_GMII 1 /* MII PHY management */
370 #define CONFIG_MPC83XX_TSEC1 1
371 #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
372 #define CONFIG_MPC83XX_TSEC2 1
373 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
374 #define TSEC1_PHY_ADDR 0
375 #define TSEC2_PHY_ADDR 1
376 #define TSEC1_PHYIDX 0
377 #define TSEC2_PHYIDX 0
379 /* Options are: TSEC[0-1] */
380 #define CONFIG_ETHPRIME "TSEC0"
382 #endif /* CONFIG_TSEC_ENET */
388 #define CFG_ENV_IS_IN_FLASH 1
389 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
390 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
391 #define CFG_ENV_SIZE 0x2000
393 #define CFG_NO_FLASH 1 /* Flash is not usable now */
394 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
395 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
396 #define CFG_ENV_SIZE 0x2000
399 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
400 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
402 #if defined(CFG_RAMBOOT)
403 #if defined(CONFIG_PCI)
404 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
412 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
420 #if defined(CONFIG_PCI)
421 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
426 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
434 #include <cmd_confdefs.h>
436 #undef CONFIG_WATCHDOG /* watchdog disabled */
439 * Miscellaneous configurable options
441 #define CFG_LONGHELP /* undef to save memory */
442 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
443 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
445 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
446 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
448 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
451 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
452 #define CFG_MAXARGS 16 /* max number of command args */
453 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
454 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
457 * For booting Linux, the board info and command line data
458 * have to be in the first 8 MB of memory, since this is
459 * the maximum mapped by the Linux kernel during initialization.
461 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
463 /* Cache Configuration */
464 #define CFG_DCACHE_SIZE 32768
465 #define CFG_CACHELINE_SIZE 32
466 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
467 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
470 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
472 #define CFG_HRCW_LOW (\
473 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
474 HRCWL_DDR_TO_SCB_CLK_1X1 |\
475 HRCWL_CSB_TO_CLKIN_4X1 |\
477 HRCWL_CORE_TO_CSB_2X1)
479 #if defined(PCI_64BIT)
480 #define CFG_HRCW_HIGH (\
483 HRCWH_PCI1_ARBITER_ENABLE |\
484 HRCWH_PCI2_ARBITER_DISABLE |\
486 HRCWH_FROM_0X00000100 |\
487 HRCWH_BOOTSEQ_DISABLE |\
488 HRCWH_SW_WATCHDOG_DISABLE |\
489 HRCWH_ROM_LOC_LOCAL_16BIT |\
490 HRCWH_TSEC1M_IN_GMII |\
491 HRCWH_TSEC2M_IN_GMII )
493 #define CFG_HRCW_HIGH (\
496 HRCWH_PCI1_ARBITER_ENABLE |\
497 HRCWH_PCI2_ARBITER_ENABLE |\
499 HRCWH_FROM_0X00000100 |\
500 HRCWH_BOOTSEQ_DISABLE |\
501 HRCWH_SW_WATCHDOG_DISABLE |\
502 HRCWH_ROM_LOC_LOCAL_16BIT |\
503 HRCWH_TSEC1M_IN_GMII |\
504 HRCWH_TSEC2M_IN_GMII )
507 #define CFG_HID0_INIT 0x000000000
509 #define CFG_HID0_FINAL CFG_HID0_INIT
511 /* #define CFG_HID0_FINAL (\
512 HID0_ENABLE_INSTRUCTION_CACHE |\
514 HID0_ENABLE_ADDRESS_BROADCAST ) */
516 #define CFG_HID2 0x000000000
519 * Internal Definitions
523 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
524 #define BOOTFLAG_WARM 0x02 /* Software reboot */
526 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
527 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
528 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
532 * Environment Configuration
535 #if defined(CONFIG_TSEC_ENET)
536 #define CONFIG_ETHADDR 00:04:9f:11:22:33
537 #define CONFIG_HAS_ETH1
538 #define CONFIG_ETH1ADDR 00:E0:0C:00:7D:01
541 #define CONFIG_IPADDR 192.168.1.253
543 #define CONFIG_HOSTNAME unknown
544 #define CONFIG_ROOTPATH /nfsroot
545 #define CONFIG_BOOTFILE your.uImage
547 #define CONFIG_SERVERIP 192.168.1.1
548 #define CONFIG_GATEWAYIP 192.168.1.1
549 #define CONFIG_NETMASK 255.255.255.0
551 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
553 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
554 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
556 #define CONFIG_BAUDRATE 115200
559 #define CONFIG_EXTRA_ENV_SETTINGS \
561 "consoledev=ttyS0\0" \
562 "ramdiskaddr=400000\0" \
563 "ramdiskfile=ramfs.83xx\0"
565 #define CONFIG_NFSBOOTCOMMAND \
566 "setenv bootargs root=/dev/nfs rw " \
567 "nfsroot=$serverip:$rootpath " \
568 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
569 "console=$consoledev,$baudrate $othbootargs;" \
570 "tftp $loadaddr $bootfile;" \
573 #define CONFIG_RAMBOOTCOMMAND \
574 "setenv bootargs root=/dev/ram rw " \
575 "console=$consoledev,$baudrate $othbootargs;" \
576 "tftp $ramdiskaddr $ramdiskfile;" \
577 "tftp $loadaddr $bootfile;" \
578 "bootm $loadaddr $ramdiskaddr"
580 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
582 #endif /* __CONFIG_H */