2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * mpc8540ads board configuration file
28 * Please refer to doc/README.mpc85xx for more info.
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
37 /* High Level Configuration Options */
38 #define CONFIG_BOOKE 1 /* BOOKE */
39 #define CONFIG_E500 1 /* BOOKE e500 family */
40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41 #define CONFIG_MPC8540 1 /* MPC8540 specific */
42 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
44 #ifndef CONFIG_HAS_FEC
45 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */
49 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
50 #define CONFIG_TSEC_ENET /* tsec ethernet support */
51 #define CONFIG_ENV_OVERWRITE
52 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
57 * Two valid values are:
61 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
62 * is likely the desired value here, so that is now the default.
63 * The board, however, can run at 66MHz. In any event, this value
64 * must match the settings of some switches. Details can be found
65 * in the README.mpc85xxads.
67 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
68 * 33MHz to accommodate, based on a PCI pin.
69 * Note that PCI-X won't work at 33MHz.
72 #ifndef CONFIG_SYS_CLK_FREQ
73 #define CONFIG_SYS_CLK_FREQ 33000000
78 * These can be toggled for performance analysis, otherwise use default.
80 #define CONFIG_L2_CACHE /* toggle L2 cache */
81 #define CONFIG_BTB /* toggle branch predition */
83 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
84 #define CONFIG_SYS_MEMTEST_END 0x00400000
88 * Base addresses -- Note these are effective addresses where the
89 * actual resources get mapped (not physical addresses)
91 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
92 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
93 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
94 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
97 #define CONFIG_FSL_DDR1
98 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
99 #define CONFIG_DDR_SPD
100 #undef CONFIG_FSL_DDR_INTERACTIVE
102 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
107 #define CONFIG_NUM_DDR_CONTROLLERS 1
108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
109 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
111 /* I2C addresses of SPD EEPROMs */
112 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
114 /* These are used when DDR doesn't use SPD. */
115 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
116 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
117 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
118 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
119 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
120 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
121 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
122 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
125 * SDRAM on the Local Bus
127 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
128 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
130 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
131 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
133 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
134 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
135 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
136 #undef CONFIG_SYS_FLASH_CHECKSUM
137 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
138 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
140 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
142 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
143 #define CONFIG_SYS_RAMBOOT
145 #undef CONFIG_SYS_RAMBOOT
148 #define CONFIG_FLASH_CFI_DRIVER
149 #define CONFIG_SYS_FLASH_CFI
150 #define CONFIG_SYS_FLASH_EMPTY_INFO
152 #undef CONFIG_CLOCKS_IN_MHZ
156 * Local Bus Definitions
160 * Base Register 2 and Option Register 2 configure SDRAM.
161 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
164 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
165 * port-size = 32-bits = BR2[19:20] = 11
166 * no parity checking = BR2[21:22] = 00
167 * SDRAM for MSEL = BR2[24:26] = 011
170 * 0 4 8 12 16 20 24 28
171 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
173 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
174 * FIXME: the top 17 bits of BR2.
177 #define CONFIG_SYS_BR2_PRELIM 0xf0001861
180 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
183 * 64MB mask for AM, OR2[0:7] = 1111 1100
184 * XAM, OR2[17:18] = 11
185 * 9 columns OR2[19-21] = 010
186 * 13 rows OR2[23-25] = 100
187 * EAD set for extra time OR[31] = 1
189 * 0 4 8 12 16 20 24 28
190 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
193 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
195 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
196 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
197 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
198 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
200 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
211 * SDRAM Controller configuration sequence.
213 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
214 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
215 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
216 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
217 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
221 * 32KB, 8-bit wide for ADS config reg
223 #define CONFIG_SYS_BR4_PRELIM 0xf8000801
224 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
225 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
227 #define CONFIG_SYS_INIT_RAM_LOCK 1
228 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
229 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
231 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
232 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
233 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
235 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
236 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
239 #define CONFIG_CONS_INDEX 1
240 #undef CONFIG_SERIAL_SOFTWARE_FIFO
241 #define CONFIG_SYS_NS16550
242 #define CONFIG_SYS_NS16550_SERIAL
243 #define CONFIG_SYS_NS16550_REG_SIZE 1
244 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
246 #define CONFIG_SYS_BAUDRATE_TABLE \
247 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
249 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
250 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
252 /* Use the HUSH parser */
253 #define CONFIG_SYS_HUSH_PARSER
254 #ifdef CONFIG_SYS_HUSH_PARSER
255 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
258 /* pass open firmware flat tree */
259 #define CONFIG_OF_LIBFDT 1
260 #define CONFIG_OF_BOARD_SETUP 1
261 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
263 #define CONFIG_SYS_64BIT_VSPRINTF 1
264 #define CONFIG_SYS_64BIT_STRTOUL 1
269 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
270 #define CONFIG_HARD_I2C /* I2C with hardware support*/
271 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
272 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
273 #define CONFIG_SYS_I2C_SLAVE 0x7F
274 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
275 #define CONFIG_SYS_I2C_OFFSET 0x3000
278 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
279 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
280 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
281 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
285 * Memory space is mapped 1-1, but I/O space must start from 0.
287 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
288 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
289 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
290 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
291 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
292 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
293 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
294 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
296 #if defined(CONFIG_PCI)
298 #define CONFIG_NET_MULTI
299 #define CONFIG_PCI_PNP /* do pci plug-and-play */
301 #undef CONFIG_EEPRO100
304 #if !defined(CONFIG_PCI_PNP)
305 #define PCI_ENET0_IOADDR 0xe0000000
306 #define PCI_ENET0_MEMADDR 0xe0000000
307 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
310 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
311 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
313 #endif /* CONFIG_PCI */
316 #if defined(CONFIG_TSEC_ENET)
318 #ifndef CONFIG_NET_MULTI
319 #define CONFIG_NET_MULTI 1
322 #define CONFIG_MII 1 /* MII PHY management */
323 #define CONFIG_TSEC1 1
324 #define CONFIG_TSEC1_NAME "TSEC0"
325 #define CONFIG_TSEC2 1
326 #define CONFIG_TSEC2_NAME "TSEC1"
327 #define TSEC1_PHY_ADDR 0
328 #define TSEC2_PHY_ADDR 1
329 #define TSEC1_PHYIDX 0
330 #define TSEC2_PHYIDX 0
331 #define TSEC1_FLAGS TSEC_GIGABIT
332 #define TSEC2_FLAGS TSEC_GIGABIT
336 #define CONFIG_MPC85XX_FEC 1
337 #define CONFIG_MPC85XX_FEC_NAME "FEC"
338 #define FEC_PHY_ADDR 3
343 /* Options are: TSEC[0-1], FEC */
344 #define CONFIG_ETHPRIME "TSEC0"
346 #endif /* CONFIG_TSEC_ENET */
352 #ifndef CONFIG_SYS_RAMBOOT
353 #define CONFIG_ENV_IS_IN_FLASH 1
354 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
355 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
356 #define CONFIG_ENV_SIZE 0x2000
358 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
359 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
360 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
361 #define CONFIG_ENV_SIZE 0x2000
364 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
365 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
371 #define CONFIG_BOOTP_BOOTFILESIZE
372 #define CONFIG_BOOTP_BOOTPATH
373 #define CONFIG_BOOTP_GATEWAY
374 #define CONFIG_BOOTP_HOSTNAME
378 * Command line configuration.
380 #include <config_cmd_default.h>
382 #define CONFIG_CMD_PING
383 #define CONFIG_CMD_I2C
384 #define CONFIG_CMD_ELF
385 #define CONFIG_CMD_IRQ
386 #define CONFIG_CMD_SETEXPR
388 #if defined(CONFIG_PCI)
389 #define CONFIG_CMD_PCI
392 #if defined(CONFIG_SYS_RAMBOOT)
393 #undef CONFIG_CMD_SAVEENV
394 #undef CONFIG_CMD_LOADS
398 #undef CONFIG_WATCHDOG /* watchdog disabled */
401 * Miscellaneous configurable options
403 #define CONFIG_SYS_LONGHELP /* undef to save memory */
404 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
405 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
406 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
408 #if defined(CONFIG_CMD_KGDB)
409 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
411 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
414 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
415 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
416 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
417 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
420 * For booting Linux, the board info and command line data
421 * have to be in the first 8 MB of memory, since this is
422 * the maximum mapped by the Linux kernel during initialization.
424 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
427 * Internal Definitions
431 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
432 #define BOOTFLAG_WARM 0x02 /* Software reboot */
434 #if defined(CONFIG_CMD_KGDB)
435 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
436 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
441 * Environment Configuration
444 /* The mac addresses for all ethernet interface */
445 #if defined(CONFIG_TSEC_ENET)
446 #define CONFIG_HAS_ETH0
447 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
448 #define CONFIG_HAS_ETH1
449 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
450 #define CONFIG_HAS_ETH2
451 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
454 #define CONFIG_IPADDR 192.168.1.253
456 #define CONFIG_HOSTNAME unknown
457 #define CONFIG_ROOTPATH /nfsroot
458 #define CONFIG_BOOTFILE your.uImage
460 #define CONFIG_SERVERIP 192.168.1.1
461 #define CONFIG_GATEWAYIP 192.168.1.1
462 #define CONFIG_NETMASK 255.255.255.0
464 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
466 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
467 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
469 #define CONFIG_BAUDRATE 115200
471 #define CONFIG_EXTRA_ENV_SETTINGS \
473 "consoledev=ttyS0\0" \
474 "ramdiskaddr=1000000\0" \
475 "ramdiskfile=your.ramdisk.u-boot\0" \
477 "fdtfile=your.fdt.dtb\0"
479 #define CONFIG_NFSBOOTCOMMAND \
480 "setenv bootargs root=/dev/nfs rw " \
481 "nfsroot=$serverip:$rootpath " \
482 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
483 "console=$consoledev,$baudrate $othbootargs;" \
484 "tftp $loadaddr $bootfile;" \
485 "tftp $fdtaddr $fdtfile;" \
486 "bootm $loadaddr - $fdtaddr"
488 #define CONFIG_RAMBOOTCOMMAND \
489 "setenv bootargs root=/dev/ram rw " \
490 "console=$consoledev,$baudrate $othbootargs;" \
491 "tftp $ramdiskaddr $ramdiskfile;" \
492 "tftp $loadaddr $bootfile;" \
493 "tftp $fdtaddr $fdtfile;" \
494 "bootm $loadaddr $ramdiskaddr $fdtaddr"
496 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
498 #endif /* __CONFIG_H */