2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * mpc8544ds board configuration file
14 /* High Level Configuration Options */
15 #define CONFIG_BOOKE 1 /* BOOKE */
16 #define CONFIG_E500 1 /* BOOKE e500 family */
17 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
18 #define CONFIG_MPC8544 1
19 #define CONFIG_MPC8544DS 1
21 #ifndef CONFIG_SYS_TEXT_BASE
22 #define CONFIG_SYS_TEXT_BASE 0xfff80000
25 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
26 #define CONFIG_PCI1 1 /* PCI controller 1 */
27 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
28 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
29 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
30 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
31 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
32 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
35 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
36 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
38 #define CONFIG_TSEC_ENET /* tsec ethernet support */
39 #define CONFIG_ENV_OVERWRITE
40 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
43 extern unsigned long get_board_sys_clk(unsigned long dummy);
45 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
48 * These can be toggled for performance analysis, otherwise use default.
50 #define CONFIG_L2_CACHE /* toggle L2 cache */
51 #define CONFIG_BTB /* toggle branch predition */
54 * Only possible on E500 Version 2 or newer cores.
56 #define CONFIG_ENABLE_36BIT_PHYS 1
58 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
59 #define CONFIG_SYS_MEMTEST_END 0x00400000
60 #define CONFIG_PANIC_HANG /* do not reset board on panic */
62 #define CONFIG_SYS_CCSRBAR 0xe0000000
63 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
66 #define CONFIG_FSL_DDR2
67 #undef CONFIG_FSL_DDR_INTERACTIVE
68 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
69 #define CONFIG_DDR_SPD
71 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
72 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
74 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
75 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
76 #define CONFIG_VERY_BIG_RAM
78 #define CONFIG_NUM_DDR_CONTROLLERS 1
79 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
80 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
82 /* I2C addresses of SPD EEPROMs */
83 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
85 /* Make sure required options are set */
86 #ifndef CONFIG_SPD_EEPROM
87 #error ("CONFIG_SPD_EEPROM is required")
90 #undef CONFIG_CLOCKS_IN_MHZ
95 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
97 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
99 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
101 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
102 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
106 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
107 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
109 * Localbus non-cacheable
111 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
112 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
113 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
118 * Local Bus Definitions
120 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
122 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
124 #define CONFIG_SYS_BR0_PRELIM 0xff801001
125 #define CONFIG_SYS_BR1_PRELIM 0xfe801001
127 #define CONFIG_SYS_OR0_PRELIM 0xff806e65
128 #define CONFIG_SYS_OR1_PRELIM 0xff806e65
130 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
132 #define CONFIG_SYS_FLASH_QUIET_TEST
133 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
134 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
135 #undef CONFIG_SYS_FLASH_CHECKSUM
136 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
137 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
138 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
140 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
142 #define CONFIG_FLASH_CFI_DRIVER
143 #define CONFIG_SYS_FLASH_CFI
144 #define CONFIG_SYS_FLASH_EMPTY_INFO
146 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
148 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
149 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
151 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
152 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
154 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
155 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */
156 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
157 #define PIXIS_VER 0x1 /* Board version at offset 1 */
158 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
159 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
160 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
162 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
163 #define PIXIS_VCTL 0x10 /* VELA Control Register */
164 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
165 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
166 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
167 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
168 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
169 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
170 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
171 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
172 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
173 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
174 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
175 #define PIXIS_VSPEED2_TSEC1SER 0x2
176 #define PIXIS_VSPEED2_TSEC3SER 0x1
177 #define PIXIS_VCFGEN1_TSEC1SER 0x20
178 #define PIXIS_VCFGEN1_TSEC3SER 0x40
179 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
180 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
183 #define CONFIG_SYS_INIT_RAM_LOCK 1
184 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
185 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
188 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
189 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
191 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
192 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
194 /* Serial Port - controlled on board with jumper J8
198 #define CONFIG_CONS_INDEX 1
199 #define CONFIG_SYS_NS16550
200 #define CONFIG_SYS_NS16550_SERIAL
201 #define CONFIG_SYS_NS16550_REG_SIZE 1
202 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
204 #define CONFIG_SYS_BAUDRATE_TABLE \
205 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
207 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
208 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
210 /* Use the HUSH parser */
211 #define CONFIG_SYS_HUSH_PARSER
213 /* pass open firmware flat tree */
214 #define CONFIG_OF_LIBFDT 1
215 #define CONFIG_OF_BOARD_SETUP 1
216 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
219 #define CONFIG_SYS_I2C
220 #define CONFIG_SYS_I2C_FSL
221 #define CONFIG_SYS_FSL_I2C_SPEED 400000
222 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
223 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
224 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
225 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
229 * Memory space is mapped 1-1, but I/O space must start from 0.
231 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
232 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
233 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
234 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
236 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
237 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
238 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
239 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
240 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
241 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
242 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
243 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
245 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
246 #define CONFIG_SYS_PCIE2_NAME "Slot 1"
247 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
248 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
249 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
250 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
251 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
252 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
253 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
254 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
256 /* controller 1, Slot 2,tgtid 2, Base address a000 */
257 #define CONFIG_SYS_PCIE1_NAME "Slot 2"
258 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
259 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
260 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
261 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
262 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
263 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
264 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
265 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
267 /* controller 3, direct to uli, tgtid 3, Base address b000 */
268 #define CONFIG_SYS_PCIE3_NAME "ULI"
269 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
270 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
271 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
272 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
273 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
274 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
275 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
276 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
277 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
278 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
279 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
280 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
282 #if defined(CONFIG_PCI)
284 /*PCIE video card used*/
285 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
287 /*PCI video card used*/
288 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
293 #if defined(CONFIG_VIDEO)
294 #define CONFIG_BIOSEMU
295 #define CONFIG_CFB_CONSOLE
296 #define CONFIG_VIDEO_SW_CURSOR
297 #define CONFIG_VGA_AS_SINGLE_DEVICE
298 #define CONFIG_ATI_RADEON_FB
299 #define CONFIG_VIDEO_LOGO
300 /*#define CONFIG_CONSOLE_CURSOR*/
301 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
304 #define CONFIG_PCI_PNP /* do pci plug-and-play */
306 #undef CONFIG_EEPRO100
308 #define CONFIG_RTL8139
310 #ifndef CONFIG_PCI_PNP
311 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
312 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
313 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
316 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
317 #define CONFIG_DOS_PARTITION
318 #define CONFIG_SCSI_AHCI
320 #ifdef CONFIG_SCSI_AHCI
321 #define CONFIG_SATA_ULI5288
322 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
323 #define CONFIG_SYS_SCSI_MAX_LUN 1
324 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
325 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
328 #endif /* CONFIG_PCI */
331 #if defined(CONFIG_TSEC_ENET)
333 #define CONFIG_MII 1 /* MII PHY management */
334 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
335 #define CONFIG_TSEC1 1
336 #define CONFIG_TSEC1_NAME "eTSEC1"
337 #define CONFIG_TSEC3 1
338 #define CONFIG_TSEC3_NAME "eTSEC3"
340 #define CONFIG_PIXIS_SGMII_CMD
341 #define CONFIG_FSL_SGMII_RISER 1
342 #define SGMII_RISER_PHY_OFFSET 0x1c
344 #define TSEC1_PHY_ADDR 0
345 #define TSEC3_PHY_ADDR 1
347 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
348 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
350 #define TSEC1_PHYIDX 0
351 #define TSEC3_PHYIDX 0
353 #define CONFIG_ETHPRIME "eTSEC1"
355 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
356 #endif /* CONFIG_TSEC_ENET */
361 #define CONFIG_ENV_IS_IN_FLASH 1
362 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
363 #define CONFIG_ENV_ADDR 0xfff80000
365 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
367 #define CONFIG_ENV_SIZE 0x2000
368 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
370 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
371 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
376 #define CONFIG_BOOTP_BOOTFILESIZE
377 #define CONFIG_BOOTP_BOOTPATH
378 #define CONFIG_BOOTP_GATEWAY
379 #define CONFIG_BOOTP_HOSTNAME
383 * Command line configuration.
385 #include <config_cmd_default.h>
387 #define CONFIG_CMD_PING
388 #define CONFIG_CMD_I2C
389 #define CONFIG_CMD_MII
390 #define CONFIG_CMD_ELF
391 #define CONFIG_CMD_IRQ
392 #define CONFIG_CMD_SETEXPR
393 #define CONFIG_CMD_REGINFO
395 #if defined(CONFIG_PCI)
396 #define CONFIG_CMD_PCI
397 #define CONFIG_CMD_NET
398 #define CONFIG_CMD_SCSI
399 #define CONFIG_CMD_EXT2
405 #define CONFIG_USB_EHCI
407 #ifdef CONFIG_USB_EHCI
408 #define CONFIG_CMD_USB
409 #define CONFIG_USB_EHCI_PCI
410 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
411 #define CONFIG_USB_STORAGE
412 #define CONFIG_PCI_EHCI_DEVICE 0
415 #undef CONFIG_WATCHDOG /* watchdog disabled */
418 * Miscellaneous configurable options
420 #define CONFIG_SYS_LONGHELP /* undef to save memory */
421 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
422 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
423 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
424 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
425 #if defined(CONFIG_CMD_KGDB)
426 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
428 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
430 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
431 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
432 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
433 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
436 * For booting Linux, the board info and command line data
437 * have to be in the first 64 MB of memory, since this is
438 * the maximum mapped by the Linux kernel during initialization.
440 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
441 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
443 #if defined(CONFIG_CMD_KGDB)
444 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
445 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
449 * Environment Configuration
452 /* The mac addresses for all ethernet interface */
453 #if defined(CONFIG_TSEC_ENET)
454 #define CONFIG_HAS_ETH0
455 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
456 #define CONFIG_HAS_ETH1
457 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
460 #define CONFIG_IPADDR 192.168.1.251
462 #define CONFIG_HOSTNAME 8544ds_unknown
463 #define CONFIG_ROOTPATH "/nfs/mpc85xx"
464 #define CONFIG_BOOTFILE "8544ds/uImage.uboot"
465 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
467 #define CONFIG_SERVERIP 192.168.1.1
468 #define CONFIG_GATEWAYIP 192.168.1.1
469 #define CONFIG_NETMASK 255.255.0.0
471 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
473 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
474 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
476 #define CONFIG_BAUDRATE 115200
478 #define CONFIG_EXTRA_ENV_SETTINGS \
480 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
481 "tftpflash=tftpboot $loadaddr $uboot; " \
482 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
484 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
486 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
488 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
490 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
492 "consoledev=ttyS0\0" \
493 "ramdiskaddr=2000000\0" \
494 "ramdiskfile=8544ds/ramdisk.uboot\0" \
496 "fdtfile=8544ds/mpc8544ds.dtb\0" \
499 #define CONFIG_NFSBOOTCOMMAND \
500 "setenv bootargs root=/dev/nfs rw " \
501 "nfsroot=$serverip:$rootpath " \
502 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
503 "console=$consoledev,$baudrate $othbootargs;" \
504 "tftp $loadaddr $bootfile;" \
505 "tftp $fdtaddr $fdtfile;" \
506 "bootm $loadaddr - $fdtaddr"
508 #define CONFIG_RAMBOOTCOMMAND \
509 "setenv bootargs root=/dev/ram rw " \
510 "console=$consoledev,$baudrate $othbootargs;" \
511 "tftp $ramdiskaddr $ramdiskfile;" \
512 "tftp $loadaddr $bootfile;" \
513 "tftp $fdtaddr $fdtfile;" \
514 "bootm $loadaddr $ramdiskaddr $fdtaddr"
516 #define CONFIG_BOOTCOMMAND \
517 "setenv bootargs root=/dev/$bdev rw " \
518 "console=$consoledev,$baudrate $othbootargs;" \
519 "tftp $loadaddr $bootfile;" \
520 "tftp $fdtaddr $fdtfile;" \
521 "bootm $loadaddr - $fdtaddr"
523 #endif /* __CONFIG_H */