include/configs/P1022DS.h

   1 /*
   2  * Copyright 2010 Freescale Semiconductor, Inc.
   3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   4  *          Timur Tabi <timur@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the Free
   8  * Software Foundation; either version 2 of the License, or (at your option)
   9  * any later version.
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 #include "../board/freescale/common/ics307_clk.h"
  16
  17 /* High Level Configuration Options */
  18 #define CONFIG_BOOKE                    /* BOOKE */
  19 #define CONFIG_E500                     /* BOOKE e500 family */
  20 #define CONFIG_MPC85xx                  /* MPC8540/60/55/41/48 */
  21 #define CONFIG_P1022
  22 #define CONFIG_P1022DS
  23 #define CONFIG_MP                       /* support multiple processors */
  24
  25 #ifndef CONFIG_SYS_TEXT_BASE
  26 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  27 #endif
  28
  29 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  30 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  31 #define CONFIG_PCIE1                    /* PCIE controler 1 (slot 1) */
  32 #define CONFIG_PCIE2                    /* PCIE controler 2 (slot 2) */
  33 #define CONFIG_PCIE3                    /* PCIE controler 3 (ULI bridge) */
  34 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  35 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
  36 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  37 #define CONFIG_SYS_HAS_SERDES           /* has SERDES */
  38
  39 #define CONFIG_PHYS_64BIT
  40 #define CONFIG_ENABLE_36BIT_PHYS
  41 #define CONFIG_ADDR_MAP
  42 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  43
  44 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  45
  46 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
  47 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  48 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  49
  50 /*
  51  * These can be toggled for performance analysis, otherwise use default.
  52  */
  53 #define CONFIG_L2_CACHE
  54 #define CONFIG_BTB
  55
  56 #define CONFIG_SYS_MEMTEST_START        0x00000000
  57 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
  58
  59 /*
  60  * Base addresses -- Note these are effective addresses where the
  61  * actual resources get mapped (not physical addresses)
  62  */
  63 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  64 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
  65 #define CONFIG_SYS_CCSRBAR_PHYS         0xfffe00000ull
  66 #define CONFIG_SYS_IMMR                 CONFIG_SYS_CCSRBAR
  67
  68 /* DDR Setup */
  69 #define CONFIG_DDR_SPD
  70 #define CONFIG_VERY_BIG_RAM
  71 #define CONFIG_FSL_DDR3
  72
  73 #ifdef CONFIG_DDR_ECC
  74 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  75 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  76 #endif
  77
  78 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  79 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  80
  81 #define CONFIG_NUM_DDR_CONTROLLERS      1
  82 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  83 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  84
  85 /* I2C addresses of SPD EEPROMs */
  86 #define CONFIG_SYS_SPD_BUS_NUM          1
  87 #define SPD_EEPROM_ADDRESS1             0x51    /* CTLR 0 DIMM 0 */
  88
  89 /*
  90  * Memory map
  91  *
  92  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
  93  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
  94  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
  95  *
  96  * Localbus cacheable (TBD)
  97  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
  98  *
  99  * Localbus non-cacheable
 100  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 101  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 102  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 103  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 104  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 105  */
 106
 107 /*
 108  * Local Bus Definitions
 109  */
 110 #define CONFIG_SYS_FLASH_BASE           0xe0000000 /* start of FLASH 128M */
 111 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 112
 113 #define CONFIG_FLASH_BR_PRELIM  \
 114         (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
 115 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
 116
 117 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 118 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 119
 120 #define CONFIG_SYS_BR1_PRELIM   \
 121         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 122 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM
 123
 124 #define CONFIG_SYS_FLASH_BANKS_LIST     \
 125         {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 126 #define CONFIG_SYS_FLASH_QUIET_TEST
 127 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 128
 129 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 130 #define CONFIG_SYS_MAX_FLASH_SECT       1024
 131
 132 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 133
 134 #define CONFIG_FLASH_CFI_DRIVER
 135 #define CONFIG_SYS_FLASH_CFI
 136 #define CONFIG_SYS_FLASH_EMPTY_INFO
 137
 138 #define CONFIG_BOARD_EARLY_INIT_F
 139 #define CONFIG_BOARD_EARLY_INIT_R
 140 #define CONFIG_MISC_INIT_R
 141 #define CONFIG_HWCONFIG
 142
 143 #define CONFIG_FSL_NGPIXIS
 144 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 145 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 146
 147 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 148 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
 149
 150 #define PIXIS_LBMAP_SWITCH      7
 151 #define PIXIS_LBMAP_MASK        0xE0
 152 #define PIXIS_LBMAP_ALTBANK     0x20
 153
 154 #define CONFIG_SYS_INIT_RAM_LOCK
 155 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
 156 #define CONFIG_SYS_INIT_RAM_END         0x00004000 /* End of used area in RAM */
 157
 158 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data */
 159 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 160         (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 161 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 162
 163 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 164 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)
 165
 166 /*
 167  * Serial Port
 168  */
 169 #define CONFIG_CONS_INDEX               1
 170 #define CONFIG_SYS_NS16550
 171 #define CONFIG_SYS_NS16550_SERIAL
 172 #define CONFIG_SYS_NS16550_REG_SIZE     1
 173 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 174
 175 #define CONFIG_SYS_BAUDRATE_TABLE       \
 176         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 177
 178 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 179 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 180
 181 /* Use the HUSH parser */
 182 #define CONFIG_SYS_HUSH_PARSER
 183 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 184
 185 /* Video */
 186 #undef CONFIG_FSL_DIU_FB
 187
 188 #ifdef CONFIG_FSL_DIU_FB
 189 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
 190 #define CONFIG_VIDEO
 191 #define CONFIG_CMD_BMP
 192 #define CONFIG_CFB_CONSOLE
 193 #define CONFIG_VGA_AS_SINGLE_DEVICE
 194 #define CONFIG_VIDEO_LOGO
 195 #define CONFIG_VIDEO_BMP_LOGO
 196 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 197 /*
 198  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 199  * disable empty flash sector detection, which is I/O-intensive.
 200  */
 201 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 202 #endif
 203
 204 /*
 205  * Pass open firmware flat tree
 206  */
 207 #define CONFIG_OF_LIBFDT
 208 #define CONFIG_OF_BOARD_SETUP
 209 #define CONFIG_OF_STDOUT_VIA_ALIAS
 210
 211 /* new uImage format support */
 212 #define CONFIG_FIT
 213 #define CONFIG_FIT_VERBOSE
 214
 215 /* I2C */
 216 #define CONFIG_FSL_I2C
 217 #define CONFIG_HARD_I2C
 218 #define CONFIG_I2C_MULTI_BUS
 219 #define CONFIG_SYS_I2C_SPEED            400000
 220 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 221 #define CONFIG_SYS_I2C_SLAVE            0x7F
 222 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
 223 #define CONFIG_SYS_I2C_OFFSET           0x3000
 224 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 225
 226 /*
 227  * I2C2 EEPROM
 228  */
 229 #define CONFIG_ID_EEPROM
 230 #define CONFIG_SYS_I2C_EEPROM_NXID
 231 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 232 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 233 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 234
 235 /*
 236  * General PCI
 237  * Memory space is mapped 1-1, but I/O space must start from 0.
 238  */
 239
 240 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 241 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 242 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 243 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 244 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 245 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 246 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 247 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 248 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 249
 250 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 251 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 252 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 253 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 254 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 255 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 256 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 257 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 258 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 259
 260 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 261 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 262 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 263 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 264 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 265 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 266 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 267 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 268 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 269
 270 #ifdef CONFIG_PCI
 271 #define CONFIG_NET_MULTI
 272 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 273 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 274 #endif
 275
 276 /* SATA */
 277 #define CONFIG_LIBATA
 278 #define CONFIG_FSL_SATA
 279
 280 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 281 #define CONFIG_SATA1
 282 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 283 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 284 #define CONFIG_SATA2
 285 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 286 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 287
 288 #ifdef CONFIG_FSL_SATA
 289 #define CONFIG_LBA48
 290 #define CONFIG_CMD_SATA
 291 #define CONFIG_DOS_PARTITION
 292 #define CONFIG_CMD_EXT2
 293 #endif
 294
 295 #define CONFIG_MMC
 296 #ifdef CONFIG_MMC
 297 #define CONFIG_CMD_MMC
 298 #define CONFIG_FSL_ESDHC
 299 #define CONFIG_GENERIC_MMC
 300 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 301 #endif
 302
 303 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 304 #define CONFIG_CMD_EXT2
 305 #define CONFIG_CMD_FAT
 306 #define CONFIG_DOS_PARTITION
 307 #endif
 308
 309 #define CONFIG_TSEC_ENET
 310 #ifdef CONFIG_TSEC_ENET
 311
 312 #define CONFIG_TSECV2
 313 #define CONFIG_NET_MULTI
 314
 315 #define CONFIG_MII                      /* MII PHY management */
 316 #define CONFIG_TSEC1            1
 317 #define CONFIG_TSEC1_NAME       "eTSEC1"
 318 #define CONFIG_TSEC2            1
 319 #define CONFIG_TSEC2_NAME       "eTSEC2"
 320
 321 #define TSEC1_PHY_ADDR          1
 322 #define TSEC2_PHY_ADDR          2
 323
 324 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 325 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 326
 327 #define TSEC1_PHYIDX            0
 328 #define TSEC2_PHYIDX            0
 329
 330 #define CONFIG_ETHPRIME         "eTSEC1"
 331
 332 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 333 #endif
 334
 335 /*
 336  * Environment
 337  */
 338 #define CONFIG_ENV_IS_IN_FLASH
 339 #define CONFIG_ENV_OVERWRITE
 340 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 341 #define CONFIG_ENV_SIZE         0x2000
 342 #define CONFIG_ENV_SECT_SIZE    0x20000
 343
 344 #define CONFIG_LOADS_ECHO
 345 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 346
 347 /*
 348  * Command line configuration.
 349  */
 350 #include <config_cmd_default.h>
 351
 352 #define CONFIG_CMD_ELF
 353 #define CONFIG_CMD_ERRATA
 354 #define CONFIG_CMD_IRQ
 355 #define CONFIG_CMD_I2C
 356 #define CONFIG_CMD_MII
 357 #define CONFIG_CMD_PING
 358 #define CONFIG_CMD_SETEXPR
 359
 360 #ifdef CONFIG_PCI
 361 #define CONFIG_CMD_PCI
 362 #define CONFIG_CMD_NET
 363 #endif
 364
 365 /*
 366  * USB
 367  */
 368 #define CONFIG_USB_EHCI
 369
 370 #ifdef CONFIG_USB_EHCI
 371 #define CONFIG_CMD_USB
 372 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 373 #define CONFIG_USB_EHCI_FSL
 374 #define CONFIG_USB_STORAGE
 375 #define CONFIG_CMD_FAT
 376 #endif
 377
 378 /*
 379  * Miscellaneous configurable options
 380  */
 381 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 382 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 383 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 384 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 385 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 386 #ifdef CONFIG_CMD_KGDB
 387 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 388 #else
 389 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 390 #endif
 391 /* Print Buffer Size */
 392 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 393 #define CONFIG_SYS_MAXARGS      16
 394 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 395 #define CONFIG_SYS_HZ           1000
 396
 397 /*
 398  * For booting Linux, the board info and command line data
 399  * have to be in the first 16 MB of memory, since this is
 400  * the maximum mapped by the Linux kernel during initialization.
 401  */
 402 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 403
 404 /*
 405  * Internal Definitions
 406  *
 407  * Boot Flags
 408  */
 409 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 410 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 411
 412 #ifdef CONFIG_CMD_KGDB
 413 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 414 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 415 #endif
 416
 417 /*
 418  * Environment Configuration
 419  */
 420
 421 #define CONFIG_HOSTNAME         p1022ds
 422 #define CONFIG_ROOTPATH         /opt/nfsroot
 423 #define CONFIG_BOOTFILE         uImage
 424 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 425
 426 #define CONFIG_LOADADDR         1000000
 427
 428 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 429 #define CONFIG_BOOTARGS
 430
 431 #define CONFIG_BAUDRATE 115200
 432
 433 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 434         "perf_mode=stable\0"                                            \
 435         "memctl_intlv_ctl=2\0"                                          \
 436         "netdev=eth0\0"                                                 \
 437         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 438         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 439                 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "     \
 440                 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "           \
 441                 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "   \
 442                 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "              \
 443                 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"  \
 444         "consoledev=ttyS0\0"                                            \
 445         "ramdiskaddr=2000000\0"                                         \
 446         "ramdiskfile=uramdisk\0"                                        \
 447         "fdtaddr=c00000\0"                                              \
 448         "fdtfile=p1022ds.dtb\0"                                         \
 449         "bdev=sda3\0"                                                   \
 450         "diuregs=md e002c000 1d\0"                                      \
 451         "dium=mw e002c01c\0"                                            \
 452         "diuerr=md e002c014 1\0"                                        \
 453         "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \
 454         "monitor=0-DVI\0"
 455
 456 #define CONFIG_HDBOOT                                   \
 457         "setenv bootargs root=/dev/$bdev rw "           \
 458         "console=$consoledev,$baudrate $othbootargs;"   \
 459         "tftp $loadaddr $bootfile;"                     \
 460         "tftp $fdtaddr $fdtfile;"                       \
 461         "bootm $loadaddr - $fdtaddr"
 462
 463 #define CONFIG_NFSBOOTCOMMAND                                           \
 464         "setenv bootargs root=/dev/nfs rw "                             \
 465         "nfsroot=$serverip:$rootpath "                                  \
 466         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 467         "console=$consoledev,$baudrate $othbootargs;"                   \
 468         "tftp $loadaddr $bootfile;"                                     \
 469         "tftp $fdtaddr $fdtfile;"                                       \
 470         "bootm $loadaddr - $fdtaddr"
 471
 472 #define CONFIG_RAMBOOTCOMMAND                                           \
 473         "setenv bootargs root=/dev/ram rw "                             \
 474         "console=$consoledev,$baudrate $othbootargs;"                   \
 475         "tftp $ramdiskaddr $ramdiskfile;"                               \
 476         "tftp $loadaddr $bootfile;"                                     \
 477         "tftp $fdtaddr $fdtfile;"                                       \
 478         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 479
 480 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 481
 482 #endif