include/configs/P2041RDB.h

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * P2041 RDB board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #define CONFIG_P2041RDB
  31 #define CONFIG_PHYS_64BIT
  32 #define CONFIG_PPC_P2041
  33
  34 #ifdef CONFIG_RAMBOOT_PBL
  35 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  36 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  37 #endif
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_BOOKE
  41 #define CONFIG_E500                     /* BOOKE e500 family */
  42 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  43 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  44 #define CONFIG_MPC85xx                  /* MPC85xx/PQ3 platform */
  45 #define CONFIG_FSL_CORENET              /* Freescale CoreNet platform */
  46 #define CONFIG_MP                       /* support multiple processors */
  47
  48 #ifndef CONFIG_SYS_TEXT_BASE
  49 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  50 #endif
  51
  52 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  53 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  54 #endif
  55
  56 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  57 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  58 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  59 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  60 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  61 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  62 #define CONFIG_PCIE3                    /* PCIE controler 3 */
  63 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  64 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  65
  66 #define CONFIG_SYS_SRIO
  67 #define CONFIG_SRIO1                    /* SRIO port 1 */
  68 #define CONFIG_SRIO2                    /* SRIO port 2 */
  69 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  70
  71 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  72
  73 #define CONFIG_ENV_OVERWRITE
  74
  75 #ifdef CONFIG_SYS_NO_FLASH
  76 #define CONFIG_ENV_IS_NOWHERE
  77 #else
  78 #define CONFIG_FLASH_CFI_DRIVER
  79 #define CONFIG_SYS_FLASH_CFI
  80 #endif
  81
  82 #if defined(CONFIG_SPIFLASH)
  83         #define CONFIG_SYS_EXTRA_ENV_RELOC
  84         #define CONFIG_ENV_IS_IN_SPI_FLASH
  85         #define CONFIG_ENV_SPI_BUS              0
  86         #define CONFIG_ENV_SPI_CS               0
  87         #define CONFIG_ENV_SPI_MAX_HZ           10000000
  88         #define CONFIG_ENV_SPI_MODE             0
  89         #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  90         #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  91         #define CONFIG_ENV_SECT_SIZE            0x10000
  92 #elif defined(CONFIG_SDCARD)
  93         #define CONFIG_SYS_EXTRA_ENV_RELOC
  94         #define CONFIG_ENV_IS_IN_MMC
  95         #define CONFIG_FSL_FIXED_MMC_LOCATION
  96         #define CONFIG_SYS_MMC_ENV_DEV          0
  97         #define CONFIG_ENV_SIZE                 0x2000
  98         #define CONFIG_ENV_OFFSET               (512 * 1097)
  99 #else
 100         #define CONFIG_ENV_IS_IN_FLASH
 101         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
 102                         - CONFIG_ENV_SECT_SIZE)
 103         #define CONFIG_ENV_SIZE         0x2000
 104         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 105 #endif
 106
 107 #ifndef __ASSEMBLY__
 108 unsigned long get_board_sys_clk(unsigned long dummy);
 109 #endif
 110 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
 111
 112 /*
 113  * These can be toggled for performance analysis, otherwise use default.
 114  */
 115 #define CONFIG_SYS_CACHE_STASHING
 116 #define CONFIG_BACKSIDE_L2_CACHE
 117 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 118 #define CONFIG_BTB                      /* toggle branch predition */
 119
 120 #define CONFIG_ENABLE_36BIT_PHYS
 121
 122 #ifdef CONFIG_PHYS_64BIT
 123 #define CONFIG_ADDR_MAP
 124 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 125 #endif
 126
 127 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 128 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 129 #define CONFIG_SYS_MEMTEST_END          0x00400000
 130 #define CONFIG_SYS_ALT_MEMTEST
 131 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 132
 133 /*
 134  *  Config the L3 Cache as L3 SRAM
 135  */
 136 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 137 #ifdef CONFIG_PHYS_64BIT
 138 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
 139                 CONFIG_RAMBOOT_TEXT_BASE)
 140 #else
 141 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 142 #endif
 143 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 144 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 145
 146 #ifdef CONFIG_PHYS_64BIT
 147 #define CONFIG_SYS_DCSRBAR              0xf0000000
 148 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 149 #endif
 150
 151 /* EEPROM */
 152 #define CONFIG_ID_EEPROM
 153 #define CONFIG_SYS_I2C_EEPROM_NXID
 154 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 155 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 157
 158 /*
 159  * DDR Setup
 160  */
 161 #define CONFIG_VERY_BIG_RAM
 162 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 163 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 164
 165 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 166 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 167
 168 #define CONFIG_DDR_SPD
 169 #define CONFIG_FSL_DDR3
 170
 171 #define CONFIG_SYS_SPD_BUS_NUM  0
 172 #define SPD_EEPROM_ADDRESS      0x52
 173 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 174
 175 /*
 176  * Local Bus Definitions
 177  */
 178
 179 /* Set the local bus clock 1/8 of platform clock */
 180 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 181
 182 #define CONFIG_SYS_FLASH_BASE           0xe8000000      /* Start of PromJet */
 183 #ifdef CONFIG_PHYS_64BIT
 184 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
 185 #else
 186 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 187 #endif
 188
 189 #define CONFIG_SYS_BR0_PRELIM \
 190                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 191 #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 192                                 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 193
 194 #define CONFIG_FSL_CPLD
 195 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 196 #ifdef CONFIG_PHYS_64BIT
 197 #define CPLD_BASE_PHYS          0xfffdf0000ull
 198 #else
 199 #define CPLD_BASE_PHYS          CPLD_BASE
 200 #endif
 201
 202 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 203 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 204
 205 #define PIXIS_LBMAP_SWITCH      7
 206 #define PIXIS_LBMAP_MASK        0xf0
 207 #define PIXIS_LBMAP_SHIFT       4
 208 #define PIXIS_LBMAP_ALTBANK     0x40
 209
 210 #define CONFIG_SYS_FLASH_QUIET_TEST
 211 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 212
 213 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 214 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 215 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 216 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 217
 218 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 219
 220 #if defined(CONFIG_RAMBOOT_PBL)
 221 #define CONFIG_SYS_RAMBOOT
 222 #endif
 223
 224 #define CONFIG_SYS_FLASH_EMPTY_INFO
 225 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 226 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 227
 228 #define CONFIG_BOARD_EARLY_INIT_F
 229 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 230 #define CONFIG_MISC_INIT_R
 231
 232 #define CONFIG_HWCONFIG
 233
 234 /* define to use L1 as initial stack */
 235 #define CONFIG_L1_INIT_RAM
 236 #define CONFIG_SYS_INIT_RAM_LOCK
 237 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 238 #ifdef CONFIG_PHYS_64BIT
 239 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 240 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 241 /* The assembler doesn't like typecast */
 242 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 243         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 244           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 245 #else
 246 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 247 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 248 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 249 #endif
 250 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 251
 252 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 253                                         GENERATED_GBL_DATA_SIZE)
 254 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 255
 256 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 257 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 258
 259 /* Serial Port - controlled on board with jumper J8
 260  * open - index 2
 261  * shorted - index 1
 262  */
 263 #define CONFIG_CONS_INDEX       1
 264 #define CONFIG_SYS_NS16550
 265 #define CONFIG_SYS_NS16550_SERIAL
 266 #define CONFIG_SYS_NS16550_REG_SIZE     1
 267 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 268
 269 #define CONFIG_SYS_BAUDRATE_TABLE       \
 270         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 271
 272 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 273 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 274 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 275 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 276
 277 /* Use the HUSH parser */
 278 #define CONFIG_SYS_HUSH_PARSER
 279 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 280
 281 /* pass open firmware flat tree */
 282 #define CONFIG_OF_LIBFDT
 283 #define CONFIG_OF_BOARD_SETUP
 284 #define CONFIG_OF_STDOUT_VIA_ALIAS
 285
 286 /* new uImage format support */
 287 #define CONFIG_FIT
 288 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 289
 290 /* I2C */
 291 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 292 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 293 #define CONFIG_I2C_MULTI_BUS
 294 #define CONFIG_I2C_CMD_TREE
 295 #define CONFIG_SYS_I2C_SPEED            400000
 296 #define CONFIG_SYS_I2C_SLAVE            0x7F
 297 #define CONFIG_SYS_I2C_OFFSET           0x118000
 298 #define CONFIG_SYS_I2C2_OFFSET          0x118100
 299
 300 /*
 301  * RapidIO
 302  */
 303 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 304 #ifdef CONFIG_PHYS_64BIT
 305 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 306 #else
 307 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 308 #endif
 309 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 310
 311 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 312 #ifdef CONFIG_PHYS_64BIT
 313 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 314 #else
 315 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 316 #endif
 317 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 318
 319 /*
 320  * eSPI - Enhanced SPI
 321  */
 322 #define CONFIG_FSL_ESPI
 323 #define CONFIG_SPI_FLASH
 324 #define CONFIG_SPI_FLASH_SPANSION
 325 #define CONFIG_CMD_SF
 326 #define CONFIG_SF_DEFAULT_SPEED         10000000
 327 #define CONFIG_SF_DEFAULT_MODE          0
 328
 329 /*
 330  * General PCI
 331  * Memory space is mapped 1-1, but I/O space must start from 0.
 332  */
 333
 334 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 335 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 336 #ifdef CONFIG_PHYS_64BIT
 337 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 338 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 339 #else
 340 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 341 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 342 #endif
 343 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 344 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 345 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 346 #ifdef CONFIG_PHYS_64BIT
 347 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 348 #else
 349 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 350 #endif
 351 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 352
 353 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 354 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 355 #ifdef CONFIG_PHYS_64BIT
 356 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 357 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 358 #else
 359 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 360 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 361 #endif
 362 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 363 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 364 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 365 #ifdef CONFIG_PHYS_64BIT
 366 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 367 #else
 368 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 369 #endif
 370 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 371
 372 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 373 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 374 #ifdef CONFIG_PHYS_64BIT
 375 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 376 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 377 #else
 378 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 379 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 380 #endif
 381 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 382 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 383 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 384 #ifdef CONFIG_PHYS_64BIT
 385 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 386 #else
 387 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 388 #endif
 389 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 390
 391 /* Qman/Bman */
 392 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 393 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 394 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 395 #ifdef CONFIG_PHYS_64BIT
 396 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 397 #else
 398 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 399 #endif
 400 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 401 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 402 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 403 #ifdef CONFIG_PHYS_64BIT
 404 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 405 #else
 406 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 407 #endif
 408 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 409
 410 #define CONFIG_SYS_DPAA_FMAN
 411 #define CONFIG_SYS_DPAA_PME
 412 /* Default address of microcode for the Linux Fman driver */
 413 #if defined(CONFIG_SPIFLASH)
 414 /*
 415  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 416  * env, so we got 0x110000.
 417  */
 418 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 419 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x110000
 420 #elif defined(CONFIG_SDCARD)
 421 /*
 422  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 423  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 424  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 425  */
 426 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 427 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (512 * 1130)
 428 #elif defined(CONFIG_NAND)
 429 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 430 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 431 #else
 432 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 433 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xEF000000
 434 #endif
 435 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 436 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 437
 438 #ifdef CONFIG_SYS_DPAA_FMAN
 439 #define CONFIG_FMAN_ENET
 440 #define CONFIG_PHYLIB_10G
 441 #define CONFIG_PHY_VITESSE
 442 #define CONFIG_PHY_TERANETICS
 443 #endif
 444
 445 #ifdef CONFIG_PCI
 446 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 447 #define CONFIG_E1000
 448
 449 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 450 #define CONFIG_DOS_PARTITION
 451 #endif  /* CONFIG_PCI */
 452
 453 /* SATA */
 454 #define CONFIG_FSL_SATA
 455 #ifdef CONFIG_FSL_SATA
 456 #define CONFIG_LIBATA
 457
 458 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 459 #define CONFIG_SATA1
 460 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 461 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 462 #define CONFIG_SATA2
 463 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 464 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 465
 466 #define CONFIG_LBA48
 467 #define CONFIG_CMD_SATA
 468 #define CONFIG_DOS_PARTITION
 469 #define CONFIG_CMD_EXT2
 470 #endif
 471
 472 #ifdef CONFIG_FMAN_ENET
 473 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 474 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 475 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 476 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 477 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 478
 479 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 480 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 481 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 482 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 483
 484 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 485
 486 #define CONFIG_SYS_TBIPA_VALUE  8
 487 #define CONFIG_MII              /* MII PHY management */
 488 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 489 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 490 #endif
 491
 492 /*
 493  * Environment
 494  */
 495 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 496 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 497
 498 /*
 499  * Command line configuration.
 500  */
 501 #include <config_cmd_default.h>
 502
 503 #define CONFIG_CMD_DHCP
 504 #define CONFIG_CMD_ELF
 505 #define CONFIG_CMD_ERRATA
 506 #define CONFIG_CMD_GREPENV
 507 #define CONFIG_CMD_IRQ
 508 #define CONFIG_CMD_I2C
 509 #define CONFIG_CMD_MII
 510 #define CONFIG_CMD_PING
 511 #define CONFIG_CMD_SETEXPR
 512
 513 #ifdef CONFIG_PCI
 514 #define CONFIG_CMD_PCI
 515 #define CONFIG_CMD_NET
 516 #endif
 517
 518 /*
 519 * USB
 520 */
 521 #define CONFIG_CMD_USB
 522 #define CONFIG_USB_STORAGE
 523 #define CONFIG_USB_EHCI
 524 #define CONFIG_USB_EHCI_FSL
 525 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 526 #define CONFIG_CMD_EXT2
 527
 528 #define CONFIG_MMC
 529
 530 #ifdef CONFIG_MMC
 531 #define CONFIG_FSL_ESDHC
 532 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 533 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 534 #define CONFIG_CMD_MMC
 535 #define CONFIG_GENERIC_MMC
 536 #define CONFIG_CMD_EXT2
 537 #define CONFIG_CMD_FAT
 538 #define CONFIG_DOS_PARTITION
 539 #endif
 540
 541 /*
 542  * Miscellaneous configurable options
 543  */
 544 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 545 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 546 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 547 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 548 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 549 #ifdef CONFIG_CMD_KGDB
 550 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 551 #else
 552 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 553 #endif
 554 /* Print Buffer Size */
 555 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 556                                 sizeof(CONFIG_SYS_PROMPT)+16)
 557 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 558 /* Boot Argument Buffer Size */
 559 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 560 #define CONFIG_SYS_HZ           1000            /* decrementer freq 1ms ticks */
 561
 562 /*
 563  * For booting Linux, the board info and command line data
 564  * have to be in the first 64 MB of memory, since this is
 565  * the maximum mapped by the Linux kernel during initialization.
 566  */
 567 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 568 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 569
 570 #ifdef CONFIG_CMD_KGDB
 571 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 572 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 573 #endif
 574
 575 /*
 576  * Environment Configuration
 577  */
 578 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 579 #define CONFIG_BOOTFILE         "uImage"
 580 #define CONFIG_UBOOTPATH        u-boot.bin
 581
 582 /* default location for tftp and bootm */
 583 #define CONFIG_LOADADDR         1000000
 584
 585 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 586
 587 #define CONFIG_BAUDRATE 115200
 588
 589 #define __USB_PHY_TYPE  utmi
 590
 591 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 592         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 593         "bank_intlv=cs0_cs1\0"                                  \
 594         "netdev=eth0\0"                                         \
 595         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                  \
 596         "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"          \
 597         "tftpflash=tftpboot $loadaddr $uboot && "               \
 598         "protect off $ubootaddr +$filesize && "                 \
 599         "erase $ubootaddr +$filesize && "                       \
 600         "cp.b $loadaddr $ubootaddr $filesize && "               \
 601         "protect on $ubootaddr +$filesize && "                  \
 602         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 603         "consoledev=ttyS0\0"                                    \
 604         "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0"             \
 605         "usb_dr_mode=host\0"                                    \
 606         "ramdiskaddr=2000000\0"                                 \
 607         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 608         "fdtaddr=c00000\0"                                      \
 609         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 610         "bdev=sda3\0"                                           \
 611         "c=ffe\0"
 612
 613 #define CONFIG_HDBOOT                                   \
 614         "setenv bootargs root=/dev/$bdev rw "           \
 615         "console=$consoledev,$baudrate $othbootargs;"   \
 616         "tftp $loadaddr $bootfile;"                     \
 617         "tftp $fdtaddr $fdtfile;"                       \
 618         "bootm $loadaddr - $fdtaddr"
 619
 620 #define CONFIG_NFSBOOTCOMMAND                   \
 621         "setenv bootargs root=/dev/nfs rw "     \
 622         "nfsroot=$serverip:$rootpath "          \
 623         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 624         "console=$consoledev,$baudrate $othbootargs;"   \
 625         "tftp $loadaddr $bootfile;"             \
 626         "tftp $fdtaddr $fdtfile;"               \
 627         "bootm $loadaddr - $fdtaddr"
 628
 629 #define CONFIG_RAMBOOTCOMMAND                           \
 630         "setenv bootargs root=/dev/ram rw "             \
 631         "console=$consoledev,$baudrate $othbootargs;"   \
 632         "tftp $ramdiskaddr $ramdiskfile;"               \
 633         "tftp $loadaddr $bootfile;"                     \
 634         "tftp $fdtaddr $fdtfile;"                       \
 635         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 636
 637 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 638
 639 #ifdef CONFIG_SECURE_BOOT
 640 #include <asm/fsl_secure_boot.h>
 641 #endif
 642
 643 #endif  /* __CONFIG_H */