2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * P2041 RDB board configuration file
30 #define CONFIG_P2041RDB
31 #define CONFIG_PHYS_64BIT
32 #define CONFIG_PPC_P2041
34 #ifdef CONFIG_RAMBOOT_PBL
35 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
39 #ifdef CONFIG_SRIOBOOT_SLAVE
40 /* Set 1M boot space */
41 #define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
42 #define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \
43 (0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR)
44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
45 #define CONFIG_SYS_NO_FLASH
48 /* High Level Configuration Options */
50 #define CONFIG_E500 /* BOOKE e500 family */
51 #define CONFIG_E500MC /* BOOKE e500mc family */
52 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
53 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
54 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
55 #define CONFIG_MP /* support multiple processors */
57 #ifndef CONFIG_SYS_TEXT_BASE
58 #define CONFIG_SYS_TEXT_BASE 0xeff80000
61 #ifndef CONFIG_RESET_VECTOR_ADDRESS
62 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
65 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
66 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
67 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
68 #define CONFIG_PCI /* Enable PCI/PCIE */
69 #define CONFIG_PCIE1 /* PCIE controler 1 */
70 #define CONFIG_PCIE2 /* PCIE controler 2 */
71 #define CONFIG_PCIE3 /* PCIE controler 3 */
72 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
73 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
75 #define CONFIG_SYS_SRIO
76 #define CONFIG_SRIO1 /* SRIO port 1 */
77 #define CONFIG_SRIO2 /* SRIO port 2 */
78 #define CONFIG_SYS_DPAA_RMAN /* RMan */
80 #define CONFIG_FSL_LAW /* Use common FSL init code */
82 #define CONFIG_ENV_OVERWRITE
84 #ifdef CONFIG_SYS_NO_FLASH
85 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIOBOOT_SLAVE)
86 #define CONFIG_ENV_IS_NOWHERE
89 #define CONFIG_FLASH_CFI_DRIVER
90 #define CONFIG_SYS_FLASH_CFI
91 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
94 #if defined(CONFIG_SPIFLASH)
95 #define CONFIG_SYS_EXTRA_ENV_RELOC
96 #define CONFIG_ENV_IS_IN_SPI_FLASH
97 #define CONFIG_ENV_SPI_BUS 0
98 #define CONFIG_ENV_SPI_CS 0
99 #define CONFIG_ENV_SPI_MAX_HZ 10000000
100 #define CONFIG_ENV_SPI_MODE 0
101 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
102 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
103 #define CONFIG_ENV_SECT_SIZE 0x10000
104 #elif defined(CONFIG_SDCARD)
105 #define CONFIG_SYS_EXTRA_ENV_RELOC
106 #define CONFIG_ENV_IS_IN_MMC
107 #define CONFIG_FSL_FIXED_MMC_LOCATION
108 #define CONFIG_SYS_MMC_ENV_DEV 0
109 #define CONFIG_ENV_SIZE 0x2000
110 #define CONFIG_ENV_OFFSET (512 * 1097)
111 #elif defined(CONFIG_NAND)
112 #define CONFIG_SYS_EXTRA_ENV_RELOC
113 #define CONFIG_ENV_IS_IN_NAND
114 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
115 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
116 #elif defined(CONFIG_SRIOBOOT_SLAVE)
117 #define CONFIG_ENV_IS_IN_REMOTE
118 #define CONFIG_ENV_ADDR 0xffe20000
119 #define CONFIG_ENV_SIZE 0x2000
120 #elif defined(CONFIG_ENV_IS_NOWHERE)
121 #define CONFIG_ENV_SIZE 0x2000
123 #define CONFIG_ENV_IS_IN_FLASH
124 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
125 - CONFIG_ENV_SECT_SIZE)
126 #define CONFIG_ENV_SIZE 0x2000
127 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
131 unsigned long get_board_sys_clk(unsigned long dummy);
133 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
136 * These can be toggled for performance analysis, otherwise use default.
138 #define CONFIG_SYS_CACHE_STASHING
139 #define CONFIG_BACKSIDE_L2_CACHE
140 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
141 #define CONFIG_BTB /* toggle branch predition */
143 #define CONFIG_ENABLE_36BIT_PHYS
145 #ifdef CONFIG_PHYS_64BIT
146 #define CONFIG_ADDR_MAP
147 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
150 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
151 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
152 #define CONFIG_SYS_MEMTEST_END 0x00400000
153 #define CONFIG_SYS_ALT_MEMTEST
154 #define CONFIG_PANIC_HANG /* do not reset board on panic */
157 * Config the L3 Cache as L3 SRAM
159 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
160 #ifdef CONFIG_PHYS_64BIT
161 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
162 CONFIG_RAMBOOT_TEXT_BASE)
164 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
166 #define CONFIG_SYS_L3_SIZE (1024 << 10)
167 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
169 #ifdef CONFIG_PHYS_64BIT
170 #define CONFIG_SYS_DCSRBAR 0xf0000000
171 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
175 #define CONFIG_ID_EEPROM
176 #define CONFIG_SYS_I2C_EEPROM_NXID
177 #define CONFIG_SYS_EEPROM_BUS_NUM 0
178 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
179 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
184 #define CONFIG_VERY_BIG_RAM
185 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
186 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
188 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
189 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
191 #define CONFIG_DDR_SPD
192 #define CONFIG_FSL_DDR3
194 #define CONFIG_SYS_SPD_BUS_NUM 0
195 #define SPD_EEPROM_ADDRESS 0x52
196 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
199 * Local Bus Definitions
202 /* Set the local bus clock 1/8 of platform clock */
203 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
205 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */
206 #ifdef CONFIG_PHYS_64BIT
207 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
209 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
212 #define CONFIG_SYS_FLASH_BR_PRELIM \
213 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
214 #define CONFIG_SYS_FLASH_OR_PRELIM \
215 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
216 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
218 #define CONFIG_FSL_CPLD
219 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
220 #ifdef CONFIG_PHYS_64BIT
221 #define CPLD_BASE_PHYS 0xfffdf0000ull
223 #define CPLD_BASE_PHYS CPLD_BASE
226 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
227 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
229 #define PIXIS_LBMAP_SWITCH 7
230 #define PIXIS_LBMAP_MASK 0xf0
231 #define PIXIS_LBMAP_SHIFT 4
232 #define PIXIS_LBMAP_ALTBANK 0x40
234 #define CONFIG_SYS_FLASH_QUIET_TEST
235 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
237 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
238 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
239 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
240 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
242 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
244 #if defined(CONFIG_RAMBOOT_PBL)
245 #define CONFIG_SYS_RAMBOOT
248 #define CONFIG_NAND_FSL_ELBC
250 #ifdef CONFIG_NAND_FSL_ELBC
251 #define CONFIG_SYS_NAND_BASE 0xffa00000
252 #ifdef CONFIG_PHYS_64BIT
253 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
255 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
258 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
259 #define CONFIG_SYS_MAX_NAND_DEVICE 1
260 #define CONFIG_MTD_NAND_VERIFY_WRITE
261 #define CONFIG_CMD_NAND
262 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
264 /* NAND flash config */
265 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
266 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
267 | BR_PS_8 /* Port Size = 8 bit */ \
268 | BR_MS_FCM /* MSEL = FCM */ \
270 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
271 | OR_FCM_PGS /* Large Page*/ \
280 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
281 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
282 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
283 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
285 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
286 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
287 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
288 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
291 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
292 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
293 #endif /* CONFIG_NAND_FSL_ELBC */
295 #define CONFIG_SYS_FLASH_EMPTY_INFO
296 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
297 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
299 #define CONFIG_BOARD_EARLY_INIT_F
300 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
301 #define CONFIG_MISC_INIT_R
303 #define CONFIG_HWCONFIG
305 /* define to use L1 as initial stack */
306 #define CONFIG_L1_INIT_RAM
307 #define CONFIG_SYS_INIT_RAM_LOCK
308 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
309 #ifdef CONFIG_PHYS_64BIT
310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
312 /* The assembler doesn't like typecast */
313 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
314 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
315 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
318 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
319 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
321 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
323 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
324 GENERATED_GBL_DATA_SIZE)
325 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
327 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
328 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
330 /* Serial Port - controlled on board with jumper J8
334 #define CONFIG_CONS_INDEX 1
335 #define CONFIG_SYS_NS16550
336 #define CONFIG_SYS_NS16550_SERIAL
337 #define CONFIG_SYS_NS16550_REG_SIZE 1
338 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
340 #define CONFIG_SYS_BAUDRATE_TABLE \
341 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
343 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
344 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
345 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
346 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
348 /* Use the HUSH parser */
349 #define CONFIG_SYS_HUSH_PARSER
351 /* pass open firmware flat tree */
352 #define CONFIG_OF_LIBFDT
353 #define CONFIG_OF_BOARD_SETUP
354 #define CONFIG_OF_STDOUT_VIA_ALIAS
356 /* new uImage format support */
358 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
361 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
362 #define CONFIG_HARD_I2C /* I2C with hardware support */
363 #define CONFIG_I2C_MULTI_BUS
364 #define CONFIG_I2C_CMD_TREE
365 #define CONFIG_SYS_I2C_SPEED 400000
366 #define CONFIG_SYS_I2C_SLAVE 0x7F
367 #define CONFIG_SYS_I2C_OFFSET 0x118000
368 #define CONFIG_SYS_I2C2_OFFSET 0x118100
373 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
374 #ifdef CONFIG_PHYS_64BIT
375 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
377 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
379 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
381 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
382 #ifdef CONFIG_PHYS_64BIT
383 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
385 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
387 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
390 * for slave u-boot IMAGE instored in master memory space,
391 * PHYS must be aligned based on the SIZE
393 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS 0xfef080000ull
394 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1 0xfff80000ull
395 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */
396 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2 0x3fff80000ull
398 * for slave UCODE and ENV instored in master memory space,
399 * PHYS must be aligned based on the SIZE
401 #define CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_MEM_PHYS 0xfef040000ull
402 #define CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_MEM_BUS 0x3ffe00000ull
403 #define CONFIG_SRIOBOOT_SLAVE_UCODE_ENV_SIZE 0x40000 /* 256K */
405 /* slave core release by master*/
406 #define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4
407 #define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */
412 #ifdef CONFIG_SRIOBOOT_SLAVE
413 /* slave port for srioboot */
414 #define CONFIG_SRIOBOOT_SLAVE_PORT0
415 /* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
416 #define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000
417 #define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
418 (0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
422 * eSPI - Enhanced SPI
424 #define CONFIG_FSL_ESPI
425 #define CONFIG_SPI_FLASH
426 #define CONFIG_SPI_FLASH_SPANSION
427 #define CONFIG_CMD_SF
428 #define CONFIG_SF_DEFAULT_SPEED 10000000
429 #define CONFIG_SF_DEFAULT_MODE 0
433 * Memory space is mapped 1-1, but I/O space must start from 0.
436 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
437 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
438 #ifdef CONFIG_PHYS_64BIT
439 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
440 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
442 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
443 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
445 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
446 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
447 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
448 #ifdef CONFIG_PHYS_64BIT
449 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
451 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
453 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
455 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
456 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
457 #ifdef CONFIG_PHYS_64BIT
458 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
459 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
461 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
462 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
464 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
465 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
466 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
467 #ifdef CONFIG_PHYS_64BIT
468 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
470 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
472 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
474 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
475 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
476 #ifdef CONFIG_PHYS_64BIT
477 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
478 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
480 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
481 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
483 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
484 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
485 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
486 #ifdef CONFIG_PHYS_64BIT
487 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
489 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
491 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
494 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
495 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
496 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
497 #ifdef CONFIG_PHYS_64BIT
498 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
500 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
502 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
503 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
504 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
505 #ifdef CONFIG_PHYS_64BIT
506 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
508 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
510 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
512 #define CONFIG_SYS_DPAA_FMAN
513 #define CONFIG_SYS_DPAA_PME
514 /* Default address of microcode for the Linux Fman driver */
515 #if defined(CONFIG_SPIFLASH)
517 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
518 * env, so we got 0x110000.
520 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
521 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
522 #elif defined(CONFIG_SDCARD)
524 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
525 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
526 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
528 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
529 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
530 #elif defined(CONFIG_NAND)
531 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
532 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
533 #elif defined(CONFIG_SRIOBOOT_SLAVE)
535 * Slave has no ucode locally, it can fetch this from remote. When implementing
536 * in two corenet boards, slave's ucode could be stored in master's memory
537 * space, the address can be mapped from slave TLB->slave LAW->
538 * slave SRIO outbound window->master inbound window->master LAW->
539 * the ucode address in master's NOR flash.
541 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
542 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
544 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
545 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
547 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
548 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
550 #ifdef CONFIG_SYS_DPAA_FMAN
551 #define CONFIG_FMAN_ENET
552 #define CONFIG_PHYLIB_10G
553 #define CONFIG_PHY_VITESSE
554 #define CONFIG_PHY_TERANETICS
558 #define CONFIG_PCI_PNP /* do pci plug-and-play */
561 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
562 #define CONFIG_DOS_PARTITION
563 #endif /* CONFIG_PCI */
566 #define CONFIG_FSL_SATA
567 #ifdef CONFIG_FSL_SATA
568 #define CONFIG_LIBATA
570 #define CONFIG_SYS_SATA_MAX_DEVICE 2
572 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
573 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
575 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
576 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
579 #define CONFIG_CMD_SATA
580 #define CONFIG_DOS_PARTITION
581 #define CONFIG_CMD_EXT2
584 #ifdef CONFIG_FMAN_ENET
585 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
586 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
587 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
588 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
589 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
591 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
592 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
593 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
594 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
596 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
598 #define CONFIG_SYS_TBIPA_VALUE 8
599 #define CONFIG_MII /* MII PHY management */
600 #define CONFIG_ETHPRIME "FM1@DTSEC1"
601 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
607 #define CONFIG_LOADS_ECHO /* echo on for serial download */
608 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
611 * Command line configuration.
613 #include <config_cmd_default.h>
615 #define CONFIG_CMD_DHCP
616 #define CONFIG_CMD_ELF
617 #define CONFIG_CMD_ERRATA
618 #define CONFIG_CMD_GREPENV
619 #define CONFIG_CMD_IRQ
620 #define CONFIG_CMD_I2C
621 #define CONFIG_CMD_MII
622 #define CONFIG_CMD_PING
623 #define CONFIG_CMD_SETEXPR
626 #define CONFIG_CMD_PCI
627 #define CONFIG_CMD_NET
633 #define CONFIG_HAS_FSL_DR_USB
634 #define CONFIG_HAS_FSL_MPH_USB
636 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
637 #define CONFIG_CMD_USB
638 #define CONFIG_USB_STORAGE
639 #define CONFIG_USB_EHCI
640 #define CONFIG_USB_EHCI_FSL
641 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
644 #define CONFIG_CMD_EXT2
649 #define CONFIG_FSL_ESDHC
650 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
651 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
652 #define CONFIG_CMD_MMC
653 #define CONFIG_GENERIC_MMC
654 #define CONFIG_CMD_EXT2
655 #define CONFIG_CMD_FAT
656 #define CONFIG_DOS_PARTITION
660 * Miscellaneous configurable options
662 #define CONFIG_SYS_LONGHELP /* undef to save memory */
663 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
664 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
665 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
666 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
667 #ifdef CONFIG_CMD_KGDB
668 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
670 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
672 /* Print Buffer Size */
673 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
674 sizeof(CONFIG_SYS_PROMPT)+16)
675 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
676 /* Boot Argument Buffer Size */
677 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
678 #define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */
681 * For booting Linux, the board info and command line data
682 * have to be in the first 64 MB of memory, since this is
683 * the maximum mapped by the Linux kernel during initialization.
685 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
686 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
688 #ifdef CONFIG_CMD_KGDB
689 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
690 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
694 * Environment Configuration
696 #define CONFIG_ROOTPATH "/opt/nfsroot"
697 #define CONFIG_BOOTFILE "uImage"
698 #define CONFIG_UBOOTPATH u-boot.bin
700 /* default location for tftp and bootm */
701 #define CONFIG_LOADADDR 1000000
703 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
705 #define CONFIG_BAUDRATE 115200
707 #define __USB_PHY_TYPE utmi
709 #define CONFIG_EXTRA_ENV_SETTINGS \
710 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
711 "bank_intlv=cs0_cs1\0" \
713 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
714 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
715 "tftpflash=tftpboot $loadaddr $uboot && " \
716 "protect off $ubootaddr +$filesize && " \
717 "erase $ubootaddr +$filesize && " \
718 "cp.b $loadaddr $ubootaddr $filesize && " \
719 "protect on $ubootaddr +$filesize && " \
720 "cmp.b $loadaddr $ubootaddr $filesize\0" \
721 "consoledev=ttyS0\0" \
722 "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \
723 "usb_dr_mode=host\0" \
724 "ramdiskaddr=2000000\0" \
725 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
727 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
731 #define CONFIG_HDBOOT \
732 "setenv bootargs root=/dev/$bdev rw " \
733 "console=$consoledev,$baudrate $othbootargs;" \
734 "tftp $loadaddr $bootfile;" \
735 "tftp $fdtaddr $fdtfile;" \
736 "bootm $loadaddr - $fdtaddr"
738 #define CONFIG_NFSBOOTCOMMAND \
739 "setenv bootargs root=/dev/nfs rw " \
740 "nfsroot=$serverip:$rootpath " \
741 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
742 "console=$consoledev,$baudrate $othbootargs;" \
743 "tftp $loadaddr $bootfile;" \
744 "tftp $fdtaddr $fdtfile;" \
745 "bootm $loadaddr - $fdtaddr"
747 #define CONFIG_RAMBOOTCOMMAND \
748 "setenv bootargs root=/dev/ram rw " \
749 "console=$consoledev,$baudrate $othbootargs;" \
750 "tftp $ramdiskaddr $ramdiskfile;" \
751 "tftp $loadaddr $bootfile;" \
752 "tftp $fdtaddr $fdtfile;" \
753 "bootm $loadaddr $ramdiskaddr $fdtaddr"
755 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
757 #ifdef CONFIG_SECURE_BOOT
758 #include <asm/fsl_secure_boot.h>
761 #endif /* __CONFIG_H */