2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5200
33 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
34 #define CONFIG_PM520 1 /* ... on PM520 board */
36 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
38 #define CONFIG_MISC_INIT_R
40 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
41 #define BOOTFLAG_WARM 0x02 /* Software reboot */
43 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
44 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
45 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
49 * Serial console configuration
51 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
52 #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
53 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
56 #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
59 * 0x40000000 - 0x4fffffff - PCI Memory
60 * 0x50000000 - 0x50ffffff - PCI IO Space
63 #define CONFIG_PCI_PNP 1
64 #define CONFIG_PCI_SCAN_SHOW 1
66 #define CONFIG_PCI_MEM_BUS 0x40000000
67 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
68 #define CONFIG_PCI_MEM_SIZE 0x10000000
70 #define CONFIG_PCI_IO_BUS 0x50000000
71 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
72 #define CONFIG_PCI_IO_SIZE 0x01000000
74 #define CONFIG_NET_MULTI 1
75 #define CONFIG_EEPRO100 1
76 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
79 #define ADD_PCI_CMD CFG_CMD_PCI
83 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
88 #define CONFIG_DOS_PARTITION
92 #define CONFIG_USB_OHCI
93 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
94 #define CONFIG_USB_STORAGE
99 #if defined(CONFIG_BOOT_ROM)
100 #define ADD_DOC_CMD 0
102 #define ADD_DOC_CMD CFG_CMD_DOC
108 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
119 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
120 #include <cmd_confdefs.h>
125 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
127 #define CONFIG_PREBOOT "echo;" \
128 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
131 #undef CONFIG_BOOTARGS
133 #define CONFIG_EXTRA_ENV_SETTINGS \
136 "nfsargs=setenv bootargs root=/dev/nfs rw " \
137 "nfsroot=$(serverip):$(rootpath)\0" \
138 "ramargs=setenv bootargs root=/dev/ram rw\0" \
139 "addip=setenv bootargs $(bootargs) " \
140 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
141 ":$(hostname):$(netdev):off panic=1\0" \
142 "flash_nfs=run nfsargs addip;" \
143 "bootm $(kernel_addr)\0" \
144 "flash_self=run ramargs addip;" \
145 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
146 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
147 "rootpath=/opt/eldk30/ppc_82xx\0" \
148 "bootfile=/tftpboot/PM520/uImage\0" \
151 #define CONFIG_BOOTCOMMAND "run flash_self"
153 #if defined(CONFIG_MPC5200)
155 * IPB Bus clocking configuration.
157 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
162 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
163 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
165 #define CFG_I2C_SPEED 100000 /* 100 kHz */
166 #define CFG_I2C_SLAVE 0x7F
169 * EEPROM configuration
171 #define CFG_I2C_EEPROM_ADDR 0x58
172 #define CFG_I2C_EEPROM_ADDR_LEN 1
173 #define CFG_EEPROM_PAGE_WRITE_BITS 4
174 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
179 #define CONFIG_RTC_PCF8563
180 #define CFG_I2C_RTC_ADDR 0x51
183 * Disk-On-Chip configuration
186 #define CFG_DOC_SHORT_TIMEOUT
187 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
189 #define CFG_DOC_SUPPORT_2000
190 #define CFG_DOC_SUPPORT_MILLENNIUM
191 #define CFG_DOC_BASE 0xE0000000
192 #define CFG_DOC_SIZE 0x00100000
194 #if defined(CONFIG_BOOT_ROM)
196 * Flash configuration (8,16 or 32 MB)
197 * TEXT base always at 0xFFF00000
198 * ENV_ADDR always at 0xFFF40000
199 * FLASH_BASE at 0xFC000000 for 32 MB
200 * 0xFD000000 for 16 MB
201 * 0xFD800000 for 8 MB
203 #define CFG_FLASH_BASE 0xfc000000
204 #define CFG_FLASH_SIZE 0x02000000
205 #define CFG_BOOTROM_BASE 0xFFF00000
206 #define CFG_BOOTROM_SIZE 0x00080000
207 #define CFG_ENV_ADDR (0xFDF00000 + 0x40000)
210 * Flash configuration (8,16 or 32 MB)
211 * TEXT base always at 0xFFF00000
212 * ENV_ADDR always at 0xFFF40000
213 * FLASH_BASE at 0xFE000000 for 32 MB
214 * 0xFF000000 for 16 MB
215 * 0xFF800000 for 8 MB
217 #define CFG_FLASH_BASE 0xfe000000
218 #define CFG_FLASH_SIZE 0x02000000
219 #define CFG_ENV_ADDR (0xFFF00000 + 0x40000)
221 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
223 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
225 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
226 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
227 #define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
228 #define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
229 #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
231 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
233 #undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
237 * Environment settings
239 #define CFG_ENV_IS_IN_FLASH 1
240 #define CFG_ENV_SIZE 0x10000
241 #define CFG_ENV_SECT_SIZE 0x40000
242 #define CONFIG_ENV_OVERWRITE 1
247 #define CFG_MBAR 0xf0000000
248 #define CFG_SDRAM_BASE 0x00000000
249 #define CFG_DEFAULT_MBAR 0x80000000
251 /* Use SRAM until RAM will be available */
252 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
253 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
256 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
257 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
258 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
260 #define CFG_MONITOR_BASE TEXT_BASE
261 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
262 # define CFG_RAMBOOT 1
265 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
266 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
267 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
270 * Ethernet configuration
272 #define CONFIG_MPC5xxx_FEC 1
274 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
276 /* #define CONFIG_FEC_10MBIT 1 */
277 #define CONFIG_PHY_ADDR 0x00
282 #define CFG_GPS_PORT_CONFIG 0x10000004
285 * Miscellaneous configurable options
287 #define CFG_LONGHELP /* undef to save memory */
288 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
289 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
290 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
292 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
294 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
295 #define CFG_MAXARGS 16 /* max number of command args */
296 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
298 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
299 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
301 #define CFG_LOAD_ADDR 0x100000 /* default load address */
303 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
306 * Various low-level settings
308 #if defined(CONFIG_MPC5200)
309 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
310 #define CFG_HID0_FINAL HID0_ICE
312 #define CFG_HID0_INIT 0
313 #define CFG_HID0_FINAL 0
316 #if defined(CONFIG_BOOT_ROM)
317 #define CFG_BOOTCS_START CFG_BOOTROM_BASE
318 #define CFG_BOOTCS_SIZE CFG_BOOTROM_SIZE
319 #define CFG_BOOTCS_CFG 0x00047800
320 #define CFG_CS0_START CFG_BOOTROM_BASE
321 #define CFG_CS0_SIZE CFG_BOOTROM_SIZE
322 #define CFG_CS1_START CFG_FLASH_BASE
323 #define CFG_CS1_SIZE CFG_FLASH_SIZE
324 #define CFG_CS1_CFG 0x0004fb00
326 #define CFG_BOOTCS_START CFG_FLASH_BASE
327 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
328 #define CFG_BOOTCS_CFG 0x0004fb00
329 #define CFG_CS0_START CFG_FLASH_BASE
330 #define CFG_CS0_SIZE CFG_FLASH_SIZE
331 #define CFG_CS1_START CFG_DOC_BASE
332 #define CFG_CS1_SIZE CFG_DOC_SIZE
333 #define CFG_CS1_CFG 0x00047800
336 #define CFG_CS_BURST 0x00000000
337 #define CFG_CS_DEADCYCLE 0x33333333
339 #define CFG_RESET_ADDRESS 0xff000000
341 /*-----------------------------------------------------------------------
343 *-----------------------------------------------------------------------
345 #define CONFIG_USB_CLOCK 0x0001BBBB
346 #define CONFIG_USB_CONFIG 0x00005000
348 /*-----------------------------------------------------------------------
349 * IDE/ATA stuff Supports IDE harddisk
350 *-----------------------------------------------------------------------
353 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
355 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
356 #undef CONFIG_IDE_LED /* LED for ide not supported */
358 #undef CONFIG_IDE_RESET /* reset for ide supported */
359 #define CONFIG_IDE_PREINIT
361 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
362 #define CFG_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
364 #define CFG_ATA_IDE0_OFFSET 0x0000
366 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
368 /* Offset for data I/O */
369 #define CFG_ATA_DATA_OFFSET (0x0060)
371 /* Offset for normal register accesses */
372 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
374 /* Offset for alternate registers */
375 #define CFG_ATA_ALT_OFFSET (0x005C)
377 /* Interval between registers */
378 #define CFG_ATA_STRIDE 4
380 #endif /* __CONFIG_H */