3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
9 * U-Boot port on RPXlite board
18 * High Level Configuration Options
23 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
24 #define CONFIG_RPXLITE 1
26 #define CONFIG_SYS_TEXT_BASE 0xfff00000
28 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
29 #undef CONFIG_8xx_CONS_SMC2
30 #undef CONFIG_8xx_CONS_NONE
31 #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
33 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
35 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
38 #undef CONFIG_BOOTARGS
39 #define CONFIG_BOOTCOMMAND \
41 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
42 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
45 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
46 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
48 #define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
50 /* enable I2C and select the hardware/software driver */
51 #define CONFIG_SYS_I2C
52 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
53 #define CONFIG_SYS_I2C_SOFT_SPEED 40000 /* 40 kHz is supposed to work */
54 #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
55 /* Software (bit-bang) I2C driver configuration */
56 #define PB_SCL 0x00000020 /* PB 26 */
57 #define PB_SDA 0x00000010 /* PB 27 */
59 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
60 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
61 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
62 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
63 #define I2C_SDA(bit) if (bit) \
64 immr->im_cpm.cp_pbdat |= PB_SDA; \
66 immr->im_cpm.cp_pbdat &= ~PB_SDA
67 #define I2C_SCL(bit) if (bit) \
68 immr->im_cpm.cp_pbdat |= PB_SCL; \
70 immr->im_cpm.cp_pbdat &= ~PB_SCL
71 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
73 /* M41T11 Serial Access Timekeeper(R) SRAM */
74 #define CONFIG_RTC_M41T11 1
75 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
76 /* play along with the linux driver */
77 #define CONFIG_SYS_M41T11_BASE_YEAR 1900
79 #undef CONFIG_WATCHDOG /* watchdog disabled */
84 #define CONFIG_BOOTP_SUBNETMASK
85 #define CONFIG_BOOTP_GATEWAY
86 #define CONFIG_BOOTP_HOSTNAME
87 #define CONFIG_BOOTP_BOOTPATH
88 #define CONFIG_BOOTP_BOOTFILESIZE
92 * Command line configuration.
94 #include <config_cmd_default.h>
98 * Miscellaneous configurable options
100 #define CONFIG_SYS_LONGHELP /* undef to save memory */
101 #if defined(CONFIG_CMD_KGDB)
102 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
104 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
106 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
107 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
108 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
110 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
111 #define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
113 #define CONFIG_SYS_RESET_ADDRESS 0x09900000
115 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
117 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
120 * Low Level Configuration Settings
121 * (address mappings, register initial values, etc.)
122 * You should know what you are doing if you make changes here.
124 /*-----------------------------------------------------------------------
125 * Internal Memory Mapped Register
127 #define CONFIG_SYS_IMMR 0xFA200000
129 /*-----------------------------------------------------------------------
130 * Definitions for initial stack pointer and data area (in DPRAM)
132 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
133 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
134 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
135 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
137 /*-----------------------------------------------------------------------
138 * Start addresses for the final memory configuration
139 * (Set up by the startup code)
140 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
142 #define CONFIG_SYS_SDRAM_BASE 0x00000000
143 #define CONFIG_SYS_FLASH_BASE 0xFFC00000
144 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
145 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
147 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */
149 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
150 #endif /* CONFIG_BZIP2 */
153 * For booting Linux, the board info and command line data
154 * have to be in the first 8 MB of memory, since this is
155 * the maximum mapped by the Linux kernel during initialization.
157 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
159 /*-----------------------------------------------------------------------
162 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
163 #define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
165 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
166 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
168 #define CONFIG_SYS_DIRECT_FLASH_TFTP
170 #define CONFIG_ENV_IS_IN_FLASH 1
171 #define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
172 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
174 #define CONFIG_ENV_OVERWRITE
176 /*-----------------------------------------------------------------------
177 * Cache Configuration
179 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
180 #if defined(CONFIG_CMD_KGDB)
181 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
184 /*-----------------------------------------------------------------------
185 * SYPCR - System Protection Control 11-9
186 * SYPCR can only be written once after reset!
187 *-----------------------------------------------------------------------
188 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
190 #if defined(CONFIG_WATCHDOG)
191 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
192 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
194 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
197 /*-----------------------------------------------------------------------
198 * SIUMCR - SIU Module Configuration 11-6
199 *-----------------------------------------------------------------------
200 * PCMCIA config., multi-function pin tri-state
202 #define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
204 /*-----------------------------------------------------------------------
205 * TBSCR - Time Base Status and Control 11-26
206 *-----------------------------------------------------------------------
207 * Clear Reference Interrupt Status, Timebase freezing enabled
209 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
211 /*-----------------------------------------------------------------------
212 * RTCSC - Real-Time Clock Status and Control Register 11-27
213 *-----------------------------------------------------------------------
215 /*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
216 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE)
218 /*-----------------------------------------------------------------------
219 * PISCR - Periodic Interrupt Status and Control 11-31
220 *-----------------------------------------------------------------------
221 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
223 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
225 /*-----------------------------------------------------------------------
226 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
227 *-----------------------------------------------------------------------
228 * Reset PLL lock status sticky bit, timer expired status bit and timer
229 * interrupt status bit
231 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
233 /* up to 50 MHz we use a 1:1 clock */
234 #define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
236 /*-----------------------------------------------------------------------
237 * SCCR - System Clock and reset Control Register 15-27
238 *-----------------------------------------------------------------------
239 * Set clock output, timebase and RTC source and divider,
240 * power management and some other internal clocks
242 #define SCCR_MASK SCCR_EBDF00
243 /* up to 50 MHz we use a 1:1 clock */
244 #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS)
246 /*-----------------------------------------------------------------------
248 *-----------------------------------------------------------------------
251 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
252 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
253 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
254 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
255 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
256 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
257 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
258 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
260 /*-----------------------------------------------------------------------
261 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
262 *-----------------------------------------------------------------------
265 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
266 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
268 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
269 #undef CONFIG_IDE_LED /* LED for ide not supported */
270 #undef CONFIG_IDE_RESET /* reset for ide not supported */
272 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
273 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
275 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
277 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
279 /* Offset for data I/O */
280 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
282 /* Offset for normal register accesses */
283 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
285 /* Offset for alternate registers */
286 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
288 /*-----------------------------------------------------------------------
290 *-----------------------------------------------------------------------
293 /*#define CONFIG_SYS_DER 0x2002000F*/
294 #define CONFIG_SYS_DER 0
297 * Init Memory Controller:
299 * BR0 and OR0 (FLASH)
302 #define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
303 #define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
305 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
306 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
308 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
309 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
312 * BR1 and OR1 (SDRAM)
315 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
316 #define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
318 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
319 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
321 #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
322 #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
324 /* RPXLITE mem setting */
325 #define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */
326 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
327 #define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
328 #define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
331 * Memory Periodic Timer Prescaler
334 /* periodic timer for refresh */
335 #define CONFIG_SYS_MAMR_PTA 58
338 * Refresh clock Prescalar
340 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8
343 * MAMR settings for SDRAM
346 /* 10 column SDRAM */
347 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
348 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
349 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
351 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
352 /* Configuration variable added by yooth. */
353 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
358 * Board Status and Control Registers
362 #define BCSR0 0xFA400000
363 #define BCSR1 0xFA400001
364 #define BCSR2 0xFA400002
365 #define BCSR3 0xFA400003
367 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
368 #define BCSR0_ENNVRAM 0x02 /* CS4# Control */
369 #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
370 #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
371 #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
372 #define BCSR0_COLTEST 0x20
373 #define BCSR0_ETHLPBK 0x40
374 #define BCSR0_ETHEN 0x80
376 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
377 #define BCSR1_PCVCTL6 0x02
378 #define BCSR1_PCVCTL5 0x04
379 #define BCSR1_PCVCTL4 0x08
380 #define BCSR1_IPB5SEL 0x10
382 #define BCSR2_ENPA5HDR 0x08 /* USB Control */
383 #define BCSR2_ENUSBCLK 0x10
384 #define BCSR2_USBPWREN 0x20
385 #define BCSR2_USBSPD 0x40
386 #define BCSR2_USBSUSP 0x80
388 #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
389 #define BCSR3_BWNVR 0x02 /* NVRAM Battery */
390 #define BCSR3_RDY_BSY 0x04 /* Flash Operation */
391 #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
392 #define BCSR3_D27 0x10 /* Dip Switch settings */
393 #define BCSR3_D26 0x20
394 #define BCSR3_D25 0x40
395 #define BCSR3_D24 0x80
397 #endif /* __CONFIG_H */