3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * board/config.h - configuration options, board specific
29 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
30 * U-BOOT port on RPXlite board
34 * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
35 * U-BOOT port on RPXlite DW version board--RPXlite_DW
43 * High Level Configuration Options
50 #define CONFIG_MPC823 1 /* This is a MPC823e CPU. */
51 #define CONFIG_RPXLITE 1 /* RPXlite DW version board */
53 #ifdef CONFIG_LCD /* with LCD controller ? */
54 #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
57 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
58 #undef CONFIG_8xx_CONS_SMC2
59 #undef CONFIG_8xx_CONS_NONE
60 #define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */
63 #define CONFIG_BOOTDELAY 12 /* autoboot after 12 seconds */
65 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
68 #undef CONFIG_BOOTARGS
69 #define CONFIG_EXTRA_ENV_SETTINGS \
71 "nfsargs=setenv bootargs console=ttyS0,9600 root=/dev/nfs rw " \
72 "nfsroot=$(serverip):$(rootpath)\0" \
73 "ramargs=setenv bootargs console=tty0 console=ttyS0,9600 " \
74 "root=/dev/ram rw\0" \
75 "addip=setenv bootargs $(bootargs) " \
76 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
77 ":$(hostname):$(netdev):off panic=1\0" \
78 "flash_nfs=run nfsargs addip;" \
79 "bootm $(kernel_addr)\0" \
80 "flash_self=run ramargs addip;" \
81 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
82 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
83 "gatewayip=172.16.115.254\0" \
84 "netmask=255.255.255.0\0" \
85 "kernel_addr=ff880000\0" \
86 "ramdisk_addr=ff980000\0" \
88 #define CONFIG_BOOTCOMMAND "run flash_self"
90 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
91 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
92 #undef CONFIG_WATCHDOG /* watchdog disabled */
93 #undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */
95 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
97 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
98 #include <cmd_confdefs.h>
101 * Miscellaneous configurable options
103 #define CFG_LONGHELP /* undef to save memory */
104 #define CFG_PROMPT "u-boot>" /* Monitor Command Prompt */
106 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
107 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
109 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
111 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
112 #define CFG_MAXARGS 16 /* max number of command args */
113 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
115 #define CFG_MEMTEST_START 0x0040000 /* memtest works on */
116 #define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
117 #define CFG_LOAD_ADDR 0x100000 /* default load address */
119 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
120 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
123 * Low Level Configuration Settings
124 * (address mappings, register initial values, etc.)
125 * You should know what you are doing if you make changes here.
127 /*-----------------------------------------------------------------------
128 * Internal Memory Mapped Register
130 #define CFG_IMMR 0xFA200000
132 /*-----------------------------------------------------------------------
133 * Definitions for initial stack pointer and data area (in DPRAM)
135 #define CFG_INIT_RAM_ADDR CFG_IMMR
136 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
137 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
138 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
139 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
141 /*-----------------------------------------------------------------------
142 * Start addresses for the final memory configuration
143 * (Set up by the startup code)
144 * Please note that CFG_SDRAM_BASE _must_ start at 0
146 #define CFG_SDRAM_BASE 0x00000000
147 #define CFG_FLASH_BASE 0xFF000000
149 #if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
150 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
152 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
154 #define CFG_MONITOR_BASE 0xFF000000
155 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
158 * For booting Linux, the board info and command line data
159 * have to be in the first 8 MB of memory, since this is
160 * the maximum mapped by the Linux kernel during initialization.
162 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
164 /*-----------------------------------------------------------------------
167 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
168 #define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
169 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
170 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
172 #ifdef CFG_ENV_IS_IN_NVRAM
173 #define CFG_ENV_ADDR 0xFA000100
174 #define CFG_ENV_SIZE 0x1000
176 #define CFG_ENV_IS_IN_FLASH
177 #define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */
178 #define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
181 /*-----------------------------------------------------------------------
182 * Cache Configuration
184 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
185 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
186 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
189 /*-----------------------------------------------------------------------
190 * SYPCR - System Protection Control 32-bit 12-35
191 * SYPCR can only be written once after reset!
192 *-----------------------------------------------------------------------
193 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
195 #if defined(CONFIG_WATCHDOG)
196 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
197 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
199 #define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
200 #endif /* We can get SYPCR: 0xFFFF0689. */
202 /*-----------------------------------------------------------------------
203 * SIUMCR - SIU Module Configuration 32-bit 12-30
204 *-----------------------------------------------------------------------
205 * PCMCIA config., multi-function pin tri-state
207 #define CFG_SIUMCR (SIUMCR_MLRC10) /* SIUMCR:0x00000800 */
209 /*---------------------------------------------------------------------
210 * TBSCR - Time Base Status and Control 16-bit 12-16
211 *---------------------------------------------------------------------
212 * Clear Reference Interrupt Status, Timebase freezing enabled
214 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
215 /* TBSCR: 0x00C3 [SAM] */
217 /*-----------------------------------------------------------------------
218 * RTCSC - Real-Time Clock Status and Control Register 16-bit 12-18
219 *-----------------------------------------------------------------------
220 * [RTC enabled but not stopped on FRZ]
222 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */
224 /*-----------------------------------------------------------------------
225 * PISCR - Periodic Interrupt Status and Control 16-bit 12-23
226 *-----------------------------------------------------------------------
227 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
228 * [Periodic timer enabled,Periodic timer interrupt disable. ]
230 #define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) /* PISCR:0x0083 */
232 /*-----------------------------------------------------------------------
233 * PLPRCR - PLL, Low-Power, and Reset Control Register 32-bit 5-7
234 *-----------------------------------------------------------------------
235 * Reset PLL lock status sticky bit, timer expired status bit and timer
236 * interrupt status bit
238 /* up to 64 MHz we use a 1:2 clock */
239 #if defined(RPXlite_64MHz)
240 #define CFG_PLPRCR ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*PLPRCR: 0x00700000. */
242 #define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
245 /*-----------------------------------------------------------------------
246 * SCCR - System Clock and reset Control Register 5-3
247 *-----------------------------------------------------------------------
248 * Set clock output, timebase and RTC source and divider,
249 * power management and some other internal clocks
251 #define SCCR_MASK SCCR_EBDF00
252 /* Up to 64MHz system clock, we use 1:2 SYSTEM/BUS ratio */
253 #define CFG_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */
255 /*-----------------------------------------------------------------------
257 *-----------------------------------------------------------------------
259 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
260 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
261 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
262 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
263 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
264 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
265 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
266 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
268 /*-----------------------------------------------------------------------
269 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
270 *-----------------------------------------------------------------------
272 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
274 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
275 #undef CONFIG_IDE_LED /* LED for ide not supported */
276 #undef CONFIG_IDE_RESET /* reset for ide not supported */
278 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
279 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
281 #define CFG_ATA_IDE0_OFFSET 0x0000
282 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
284 /* Offset for data I/O */
285 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
287 /* Offset for normal register accesses */
288 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
290 /* Offset for alternate registers */
291 #define CFG_ATA_ALT_OFFSET 0x0100
296 * Init Memory Controller:
298 * BR0 and OR0 (FLASH)
300 #define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base */
301 #define CFG_PRELIM_OR_AM 0xFC000000 /* OR addr mask */
303 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */
304 #define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI)
305 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
306 #define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
309 * BR1 and OR1 (SDRAM)
312 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
313 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB in system */
315 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
316 #define CFG_OR_TIMING_SDRAM 0x00000E00
317 #define CFG_OR_AM_SDRAM (-(SDRAM_MAX_SIZE & OR_AM_MSK))
318 #define CFG_OR1_PRELIM ( CFG_OR_AM_SDRAM | CFG_OR_TIMING_SDRAM )
319 #define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
321 /* RPXlite mem setting */
322 #define CFG_BR3_PRELIM 0xFA400001 /* BCSR */
323 #define CFG_OR3_PRELIM 0xFF7F8900
324 #define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
325 #define CFG_OR4_PRELIM 0xFFFE0040
328 * Memory Periodic Timer Prescaler
330 /* periodic timer for refresh */
331 #if defined(RPXlite_64MHz)
332 #define CFG_MAMR_PTA 32
334 #define CFG_MAMR_PTA 20
338 * Refresh clock Prescalar
340 #define CFG_MPTPR MPTPR_PTP_DIV2
343 * MAMR settings for SDRAM
347 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
348 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
349 /* CFG_MAMR_9COL:0x20904000 @ 64MHz */
352 * Internal Definitions
356 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
357 #define BOOTFLAG_WARM 0x02 /* Software reboot */
359 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
360 /* Configuration variable added by yooth. */
361 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
365 * Board Status and Control Registers
368 #define BCSR0 0xFA400000
369 #define BCSR1 0xFA400001
370 #define BCSR2 0xFA400002
371 #define BCSR3 0xFA400003
373 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
374 #define BCSR0_ENNVRAM 0x02 /* CS4# Control */
375 #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
376 #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
377 #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
378 #define BCSR0_COLTEST 0x20
379 #define BCSR0_ETHLPBK 0x40
380 #define BCSR0_ETHEN 0x80
382 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
383 #define BCSR1_PCVCTL6 0x02
384 #define BCSR1_PCVCTL5 0x04
385 #define BCSR1_PCVCTL4 0x08
386 #define BCSR1_IPB5SEL 0x10
388 #define BCSR1_SMC1CTS 0x40 /* Added by SAM. */
389 #define BCSR1_SMC1TRS 0x80 /* Added by SAM. */
391 #define BCSR2_ENRTCIRQ 0x01 /* Added by SAM. */
392 #define BCSR2_ENBRG1 0x04 /* Added by SAM. */
394 #define BCSR2_ENPA5HDR 0x08 /* USB Control */
395 #define BCSR2_ENUSBCLK 0x10
396 #define BCSR2_USBPWREN 0x20
397 #define BCSR2_USBSPD 0x40
398 #define BCSR2_USBSUSP 0x80
400 #define BCSR3_BWKAPWR 0x01 /* Changed by SAM. Backup battery situation */
401 #define BCSR3_IRQRTC 0x02 /* Changed by SAM. NVRAM Battery */
402 #define BCSR3_RDY_BSY 0x04 /* Changed by SAM. Flash Operation */
403 #define BCSR3_MPLX_LIN 0x08 /* Changed by SAM. Linear or Multiplexed address Mode */
405 #define BCSR3_D27 0x10 /* Dip Switch settings */
406 #define BCSR3_D26 0x20
407 #define BCSR3_D25 0x40
408 #define BCSR3_D24 0x80
411 * Environment setting
413 #define CONFIG_ETHADDR 00:10:EC:00:37:5B
414 #define CONFIG_IPADDR 172.16.115.7
415 #define CONFIG_SERVERIP 172.16.115.6
416 #define CONFIG_ROOTPATH /workspace/myfilesystem/target/
417 #define CONFIG_BOOTFILE uImage.rpxusb
419 #endif /* __CONFIG_H */