3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
7 * TOP5200 differences from IceCube:
8 * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
9 * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
10 * 1 SDRAM/DDRAM Bank up to 256 MB
11 * local VPD I2C Bus is software driven and uses
12 * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
13 * FLASH is re-located at 0xff000000
14 * Internal regs are at 0xf0000000
15 * Reset jumps to 0x00000100
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40 * High Level Configuration Options
44 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
45 #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
46 #define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
48 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
50 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
51 #define BOOTFLAG_WARM 0x02 /* Software reboot */
53 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
54 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
55 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
59 * Serial console configuration
61 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
62 #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
63 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
66 #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
69 * 0x40000000 - 0x4fffffff - PCI Memory
70 * 0x50000000 - 0x50ffffff - PCI IO Space
73 # define CONFIG_PCI_PNP 1
74 # define CONFIG_PCI_SCAN_SHOW 1
76 # define CONFIG_PCI_MEM_BUS 0x40000000
77 # define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
78 # define CONFIG_PCI_MEM_SIZE 0x10000000
80 # define CONFIG_PCI_IO_BUS 0x50000000
81 # define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
82 # define CONFIG_PCI_IO_SIZE 0x01000000
84 # define ADD_PCI_CMD CFG_CMD_PCI
86 #else /* no Evaluation board */
88 # define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
93 #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
95 # define CONFIG_USB_OHCI
96 # define CONFIG_USB_CLOCK 0x0001bbbb
97 # define CONFIG_USB_CONFIG 0x00005000
98 # define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
99 # define CONFIG_DOS_PARTITION
100 # define CONFIG_USB_STORAGE
104 # define ADD_USB_CMD 0
109 #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
111 # define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT
112 # define CONFIG_DOS_PARTITION
116 # define ADD_IDE_CMD 0
123 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
139 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
140 #include <cmd_confdefs.h>
143 * MUST be low boot - HIGHBOOT is not supported anymore
145 #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
146 # define CFG_LOWBOOT 1
147 # define CFG_LOWBOOT16 1
149 # error "TEXT_BASE must be 0xff000000"
155 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
157 #define CONFIG_PREBOOT "echo;" \
158 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
161 #undef CONFIG_BOOTARGS
163 #define CONFIG_EXTRA_ENV_SETTINGS \
165 "nfsargs=setenv bootargs root=/dev/nfs rw " \
166 "nfsroot=$(serverip):$(rootpath)\0" \
167 "ramargs=setenv bootargs root=/dev/ram rw\0" \
168 "addip=setenv bootargs $(bootargs) " \
169 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
170 ":$(hostname):$(netdev):off panic=1\0" \
171 "flash_nfs=run nfsargs addip;" \
172 "bootm $(kernel_addr)\0" \
173 "flash_self=run ramargs addip;" \
174 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
175 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
176 "rootpath=/opt/eldk/ppc_82xx\0" \
177 "bootfile=/tftpboot/MPC5200/uImage\0" \
180 #define CONFIG_BOOTCOMMAND "run flash_self"
183 * IPB Bus clocking configuration.
185 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
191 * EEPROM configuration
193 #define CFG_EEPROM_PAGE_WRITE_BITS 3
194 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
196 #define CFG_I2C_EEPROM_ADDR_LEN 2
197 #define CFG_EEPROM_SIZE 0x2000
199 #define CONFIG_ENV_OVERWRITE
200 #define CONFIG_MISC_INIT_R
202 #undef CONFIG_HARD_I2C /* I2C with hardware support */
203 #define CONFIG_SOFT_I2C 1 /* I2C with softwate support */
205 #if defined (CONFIG_SOFT_I2C)
208 # define GPIOE0 *((volatile uchar*)(CFG_MBAR+0x0c00))
209 # define DDR0 *((volatile uchar*)(CFG_MBAR+0x0c08))
210 # define DVO0 *((volatile uchar*)(CFG_MBAR+0x0c0c))
211 # define DVI0 *((volatile uchar*)(CFG_MBAR+0x0c20))
212 # define ODE0 *((volatile uchar*)(CFG_MBAR+0x0c04))
213 # define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
214 # define I2C_READ ((DVI0&SDA0)?1:0)
215 # define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
216 # define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
217 # define I2C_DELAY {udelay(5);}
218 # define I2C_ACTIVE {DDR0|=SDA0;}
219 # define I2C_TRISTATE {DDR0&=~SDA0;}
220 # define CFG_I2C_SPEED 100000
221 # define CFG_I2C_SLAVE 0x7F
222 #define CFG_I2C_EEPROM_ADDR 0x57
223 #define CFG_I2C_FACT_ADDR 0x57
226 #if defined (CONFIG_HARD_I2C)
227 # define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
228 # define CFG_I2C_SPEED 100000 /* 100 kHz */
229 # define CFG_I2C_SLAVE 0x7F
230 #define CFG_I2C_EEPROM_ADDR 0x54
231 #define CFG_I2C_FACT_ADDR 0x54
235 * Flash configuration, expect one 16 Megabyte Bank at most
237 #define CFG_FLASH_BASE 0xff000000
238 #define CFG_FLASH_SIZE 0x01000000
239 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
240 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0)
242 #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
244 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
245 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
247 #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
250 * DRAM configuration - will be read from VPD later... TODO!
253 /* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
254 #define CFG_DRAM_DDR 0
255 #define CFG_DRAM_EMODE 0
256 #define CFG_DRAM_MODE 0x008D
257 #define CFG_DRAM_CONTROL 0x514F0000
258 #define CFG_DRAM_CONFIG1 0xC2233A00
259 #define CFG_DRAM_CONFIG2 0x88B70004
260 #define CFG_DRAM_TAP_DEL 0x08
261 #define CFG_DRAM_RAM_SIZE 0x19
264 /* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
265 #define CFG_DRAM_DDR 0
266 #define CFG_DRAM_EMODE 0
267 #define CFG_DRAM_MODE 0x00CD
268 #define CFG_DRAM_CONTROL 0x514F0000
269 #define CFG_DRAM_CONFIG1 0xD2333A00
270 #define CFG_DRAM_CONFIG2 0x8AD70004
271 #define CFG_DRAM_TAP_DEL 0x08
272 #define CFG_DRAM_RAM_SIZE 0x19
276 * Environment settings
278 #define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
279 #define CFG_ENV_OFFSET 0x1000
280 #define CFG_ENV_SIZE 0x0700
285 #define CFG_FACT_OFFSET 0x1800
286 #define CFG_FACT_SIZE 0x0800
291 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
293 #define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */
294 #define CFG_SDRAM_BASE 0x00000000
295 #define CFG_DEFAULT_MBAR 0x80000000
297 /* Use SRAM until RAM will be available */
298 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
299 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
302 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
303 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
304 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
306 #define CFG_MONITOR_BASE TEXT_BASE
307 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
308 # define CFG_RAMBOOT 1
311 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
312 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
313 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
316 * Ethernet configuration
318 #define CONFIG_MPC5xxx_FEC 1
319 #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
320 #define CONFIG_PHY_ADDR 0x1f
321 #define CONFIG_PHY_TYPE 0x79c874
323 * GPIO configuration:
324 * PSC1,2,3 predefined as UART
326 * Ethernet 100 with MD
328 #define CFG_GPS_PORT_CONFIG 0x00058444
331 * Miscellaneous configurable options
333 #define CFG_LONGHELP /* undef to save memory */
334 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
335 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
336 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
338 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
340 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
341 #define CFG_MAXARGS 16 /* max number of command args */
342 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
344 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
345 #define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
347 #define CFG_LOAD_ADDR 0x200000 /* default load address */
349 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
351 #ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
352 #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
353 #define RTC(reg) (0xf0010000+reg)
354 /* setup CS2 for M48T08. Must MAP 64kB */
355 #define CFG_CS2_START RTC(0)
356 #define CFG_CS2_SIZE 0x10000
357 /* setup CS2 configuration register: */
358 /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
359 /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
360 #define CFG_CS2_CFG 0x00047800
362 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
366 * Various low-level settings
368 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
369 #define CFG_HID0_FINAL HID0_ICE
371 #define CFG_BOOTCS_START CFG_FLASH_BASE
372 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
373 #define CFG_BOOTCS_CFG 0x00047801
374 #define CFG_CS0_START CFG_FLASH_BASE
375 #define CFG_CS0_SIZE CFG_FLASH_SIZE
377 #define CFG_CS_BURST 0x00000000
378 #define CFG_CS_DEADCYCLE 0x33333333
380 #define CFG_RESET_ADDRESS 0x7f000000
382 /*-----------------------------------------------------------------------
383 * IDE/ATA stuff Supports IDE harddisk
384 *-----------------------------------------------------------------------
387 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
389 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
390 #undef CONFIG_IDE_LED /* LED for ide not supported */
392 #define CONFIG_IDE_RESET 1
393 #define CONFIG_IDE_PREINIT
395 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
396 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
398 #define CFG_ATA_IDE0_OFFSET 0x0000
400 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
402 /* Offset for data I/O */
403 #define CFG_ATA_DATA_OFFSET (0x0060)
405 /* Offset for normal register accesses */
406 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
408 /* Offset for alternate registers */
409 #define CFG_ATA_ALT_OFFSET (0x005c)
411 /* Interval between registers */
412 #define CFG_ATA_STRIDE 4
414 #endif /* __CONFIG_H */