2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * High Level Configuration Options
35 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37 #define CONFIG_TQM5200 1 /* ... on TQM5200 module */
39 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
41 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
42 #define BOOTFLAG_WARM 0x02 /* Software reboot */
44 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
45 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
46 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
50 * Serial console configuration
52 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
53 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
54 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
57 #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
60 * 0x40000000 - 0x4fffffff - PCI Memory
61 * 0x50000000 - 0x50ffffff - PCI IO Space
64 #define CONFIG_PCI_PNP 1
65 /* #define CONFIG_PCI_SCAN_SHOW 1 */
67 #define CONFIG_PCI_MEM_BUS 0x40000000
68 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
69 #define CONFIG_PCI_MEM_SIZE 0x10000000
71 #define CONFIG_PCI_IO_BUS 0x50000000
72 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
73 #define CONFIG_PCI_IO_SIZE 0x01000000
75 #define CONFIG_NET_MULTI 1
76 #define CONFIG_EEPRO100 1
77 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
78 #define CONFIG_NS8382X 1
80 #define ADD_PCI_CMD 0 /* CFG_CMD_PCI */
84 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
89 #undef CONFIG_MAC_PARTITION
90 #if defined (CONFIG_MINIFAP)
91 #define CONFIG_DOS_PARTITION
96 #define CONFIG_USB_OHCI
97 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
98 #define CONFIG_USB_STORAGE
100 #define ADD_USB_CMD 0
104 #define CONFIG_POST (CFG_POST_MEMORY | \
109 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
110 /* preserve space for the post_word at end of on-chip SRAM */
111 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
113 #define CFG_CMD_POST_DIAG 0
117 #if defined (CONFIG_MINIFAP)
118 #define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT
120 #define ADD_IDE_CMD 0
126 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
131 CFG_CMD_POST_DIAG | \
138 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
139 #include <cmd_confdefs.h>
141 #if (TEXT_BASE == 0xFC000000) /* Boot low */
142 # define CFG_LOWBOOT 1
148 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
150 #define CONFIG_PREBOOT "echo;" \
151 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
154 #undef CONFIG_BOOTARGS
156 #if defined (CONFIG_TQM5200_AA)
157 #define CONFIG_EXTRA_ENV_SETTINGS \
159 "nfsargs=setenv bootargs root=/dev/nfs rw " \
160 "nfsroot=$(serverip):$(rootpath)\0" \
161 "ramargs=setenv bootargs root=/dev/ram rw\0" \
162 "addip=setenv bootargs $(bootargs) " \
163 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
164 ":$(hostname):$(netdev):off panic=1\0" \
165 "flash_nfs=run nfsargs addip;" \
166 "bootm $(kernel_addr)\0" \
167 "flash_self=run ramargs addip;" \
168 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
169 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
170 "rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
171 "bootfile=uImage_tqm5200_mkr\0" \
172 "load=tftp 200000 $(loadfile)\0" \
173 "load133=tftp 200000 $(loadfile133)\0" \
174 "loadfile=u-boot_tqm5200_aa_mkr.bin\0" \
175 "loadfile133=u-boot_tqm5200_aa_133_mkr.bin\0" \
176 "update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0" \
177 "serverip=172.20.5.13\0" \
180 #if defined (CONFIG_TQM5200_AB)
181 #define CONFIG_EXTRA_ENV_SETTINGS \
183 "nfsargs=setenv bootargs root=/dev/nfs rw " \
184 "nfsroot=$(serverip):$(rootpath)\0" \
185 "ramargs=setenv bootargs root=/dev/ram rw\0" \
186 "addip=setenv bootargs $(bootargs) " \
187 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
188 ":$(hostname):$(netdev):off panic=1\0" \
189 "flash_nfs=run nfsargs addip;" \
190 "bootm $(kernel_addr)\0" \
191 "flash_self=run ramargs addip;" \
192 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
193 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
194 "rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
195 "bootfile=uImage_tqm5200_mkr\0" \
196 "load=tftp 200000 $(loadfile)\0" \
197 "load133=tftp 200000 $(loadfile133)\0" \
198 "loadfile=u-boot_tqm5200_ab_mkr.bin\0" \
199 "loadfile133=u-boot_tqm5200_ab_133_mkr.bin\0" \
200 "update=protect off 1:0-1; erase 1:0-1; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-1\0" \
201 "serverip=172.20.5.13\0" \
204 #if defined (CONFIG_TQM5200_AC)
205 #define CONFIG_EXTRA_ENV_SETTINGS \
207 "nfsargs=setenv bootargs root=/dev/nfs rw " \
208 "nfsroot=$(serverip):$(rootpath)\0" \
209 "ramargs=setenv bootargs root=/dev/ram rw\0" \
210 "addip=setenv bootargs $(bootargs) " \
211 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
212 ":$(hostname):$(netdev):off panic=1\0" \
213 "flash_nfs=run nfsargs addip;" \
214 "bootm $(kernel_addr)\0" \
215 "flash_self=run ramargs addip;" \
216 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
217 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
218 "rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
219 "bootfile=uImage_tqm5200_mkr\0" \
220 "load=tftp 200000 $(loadfile)\0" \
221 "load133=tftp 200000 $(loadfile133)\0" \
222 "loadfile=u-boot_tqm5200_ac_mkr.bin\0" \
223 "loadfile133=u-boot_tqm5200_ac_133_mkr.bin\0" \
224 "update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0" \
225 "serverip=172.20.5.13\0" \
231 #define CONFIG_BOOTCOMMAND "run net_nfs"
234 * IPB Bus clocking configuration.
236 #define CFG_IPBSPEED_133 /* define for 133MHz speed */
238 #if defined(CFG_IPBSPEED_133)
240 * PCI Bus clocking configuration
242 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
243 * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
244 * been tested with a IPB Bus Clock of 66 MHz.
246 #define CFG_PCISPEED_66 /* define for 66MHz speed */
252 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
253 #if defined (CONFIG_MINIFAP)
254 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
256 #define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
260 * I2C clock frequency
262 * Please notice, that the resulting clock frequency could differ from the
263 * configured value. This is because the I2C clock is derived from system
264 * clock over a frequency divider with only a few divider values. U-boot
265 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
266 * approximation allways lies below the configured value, never above.
268 #define CFG_I2C_SPEED 100000 /* 100 kHz */
269 #define CFG_I2C_SLAVE 0x7F
272 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
273 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
274 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
275 * same configuration could be used.
277 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
278 #define CFG_I2C_EEPROM_ADDR_LEN 2
279 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
280 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
283 * HW-Monitor configuration on Mini-FAP
285 #if defined (CONFIG_MINIFAP)
286 #define CFG_I2C_HWMON_ADDR 0x2C
289 /* List of I2C addresses to be verified by POST */
290 #if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB)
291 #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
293 #elif defined (CONFIG_TQM5200_AC)
294 #define I2C_ADDR_LIST { CFG_I2C_SLAVE }
297 #if defined (CONFIG_MINIFAP)
299 #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
300 CFG_I2C_HWMON_ADDR, \
305 * Flash configuration
307 #define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
309 #if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AC)
310 #define CFG_FLASH_SIZE 0x00400000 /* 4 MByte */
311 #define CFG_MAX_FLASH_SECT 35 /* max num of sects on one chip */
313 #ifdef CONFIG_TQM5200_AB
314 #define CFG_FLASH_SIZE 0x02000000 /* 32 MByte */
315 #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
319 #if !defined(CFG_LOWBOOT)
320 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000)
321 #else /* CFG_LOWBOOT */
322 #if defined(CONFIG_TQM5200_AA) || defined(CONFIG_TQM5200_AB) || \
323 defined (CONFIG_TQM5200_AC)
324 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
326 #endif /* CFG_LOWBOOT */
327 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
329 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
330 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
334 * Environment settings
336 #define CFG_ENV_IS_IN_FLASH 1
337 #define CFG_ENV_SIZE 0x10000
338 #define CFG_ENV_SECT_SIZE 0x20000
339 #define CONFIG_ENV_OVERWRITE 1
344 #define CFG_MBAR 0xF0000000
345 #define CFG_SDRAM_BASE 0x00000000
346 #define CFG_DEFAULT_MBAR 0x80000000
348 /* Use ON-Chip SRAM until RAM will be available */
349 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
351 /* preserve space for the post_word at end of on-chip SRAM */
352 #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
354 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
358 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
359 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
360 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
362 #define CFG_MONITOR_BASE TEXT_BASE
363 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
364 # define CFG_RAMBOOT 1
367 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
368 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
369 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
372 * Ethernet configuration
374 #define CONFIG_MPC5xxx_FEC 1
376 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
378 /* #define CONFIG_FEC_10MBIT 1 */
379 #define CONFIG_PHY_ADDR 0x00
384 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
385 * Bit 0 (mask: 0x80000000): 1
386 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
387 * 00 -> No Alternatives, I2C1 is used for onboard EEPROM
388 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
390 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
391 * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
392 * 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
393 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
396 #if defined (CONFIG_MINIFAP)
397 #define CFG_GPS_PORT_CONFIG 0x93000004
399 #define CFG_GPS_PORT_CONFIG 0x83000004
405 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
408 * Miscellaneous configurable options
410 #define CFG_LONGHELP /* undef to save memory */
411 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
412 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
413 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
415 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
417 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
418 #define CFG_MAXARGS 16 /* max number of command args */
419 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
421 /* Enable an alternate, more extensive memory test */
422 #define CFG_ALT_MEMTEST
424 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
425 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
427 #define CFG_LOAD_ADDR 0x100000 /* default load address */
429 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
432 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
433 * which is normally part of the default commands (CFV_CMD_DFL)
438 * Various low-level settings
440 #if defined(CONFIG_MPC5200)
441 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
442 #define CFG_HID0_FINAL HID0_ICE
444 #define CFG_HID0_INIT 0
445 #define CFG_HID0_FINAL 0
448 #define CFG_BOOTCS_START CFG_FLASH_BASE
449 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
450 #ifdef CFG_PCISPEED_66
451 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
453 #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
455 #define CFG_CS0_START CFG_FLASH_BASE
456 #define CFG_CS0_SIZE CFG_FLASH_SIZE
459 * SRAM - Do not map below 2 GB in address space, because this area is used
460 * for SDRAM autosizing.
462 #ifdef CONFIG_TQM5200_AB
463 #define CFG_CS2_START 0xE5000000
464 #define CFG_CS2_SIZE 0x80000 /* 512 kByte */
465 #define CFG_CS2_CFG 0x0004D930
469 * Grafic controller - Do not map below 2 GB in address space, because this
470 * area is used for SDRAM autosizing.
472 #if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC)
473 #define CFG_CS1_START 0xE0000000
474 #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
475 #define CFG_CS1_CFG 0x8F48FF70
476 #define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
479 #define CFG_CS_BURST 0x00000000
480 #define CFG_CS_DEADCYCLE 0x33333333
482 #define CFG_RESET_ADDRESS 0xff000000
484 /*-----------------------------------------------------------------------
486 *-----------------------------------------------------------------------
488 #define CONFIG_USB_CLOCK 0x0001BBBB
489 #define CONFIG_USB_CONFIG 0x00001000
491 /*-----------------------------------------------------------------------
492 * IDE/ATA stuff Supports IDE harddisk
493 *-----------------------------------------------------------------------
496 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
498 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
499 #undef CONFIG_IDE_LED /* LED for ide not supported */
501 #define CONFIG_IDE_RESET /* reset for ide supported */
502 #define CONFIG_IDE_PREINIT
504 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
505 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
507 #define CFG_ATA_IDE0_OFFSET 0x0000
509 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
511 /* Offset for data I/O */
512 #define CFG_ATA_DATA_OFFSET (0x0060)
514 /* Offset for normal register accesses */
515 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
517 /* Offset for alternate registers */
518 #define CFG_ATA_ALT_OFFSET (0x005C)
520 /* Interval between registers */
521 #define CFG_ATA_STRIDE 4
523 #endif /* __CONFIG_H */