2 * Copyright 2005 DENX Software Engineering
3 * Copyright 2004 Freescale Semiconductor.
4 * (C) Copyright 2002,2003 Motorola,Inc.
5 * Xianghua Xiao <X.Xiao@motorola.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * TQM8540 board configuration file
29 * Make sure you change the MAC address and other network params first,
30 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
36 /* High Level Configuration Options */
37 #define CONFIG_BOOKE 1 /* BOOKE */
38 #define CONFIG_E500 1 /* BOOKE e500 family */
39 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
40 #define CONFIG_MPC8540 1 /* MPC8540 specific */
41 #define CONFIG_TQM8540 1 /* TQM8540 board specific */
44 #define CONFIG_TSEC_ENET /* tsec ethernet support */
45 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
46 #define CONFIG_DDR_DLL /* possible DLL fix needed */
47 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
53 * Two valid values are:
57 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
58 * is likely the desired value here, so that is now the default.
59 * The board, however, can run at 66MHz. In any event, this value
60 * must match the settings of some switches. Details can be found
61 * in the README.mpc85xxads.
64 #ifndef CONFIG_SYS_CLK_FREQ
65 #define CONFIG_SYS_CLK_FREQ 33000000
70 * These can be toggled for performance analysis, otherwise use default.
72 #define CONFIG_L2_CACHE /* toggle L2 cache */
73 #define CONFIG_BTB /* toggle branch predition */
74 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
76 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
78 #undef CFG_DRAM_TEST /* memory test, takes time */
79 #define CFG_MEMTEST_START 0x00000000 /* memtest region */
80 #define CFG_MEMTEST_END 0x10000000
84 * Base addresses -- Note these are effective addresses where the
85 * actual resources get mapped (not physical addresses)
87 #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
88 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
89 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
95 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
96 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
98 #if defined(CONFIG_SPD_EEPROM)
100 * Determine DDR configuration from I2C interface.
102 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
106 * Manually set up DDR parameters
108 #define CFG_SDRAM_SIZE 512 /* DDR is 256MB */
109 #define CFG_DDR_CS0_BNDS 0x0000001f /* 0-256MB */
110 #define CFG_DDR_CS0_CONFIG 0x80000102
111 #define CFG_DDR_TIMING_1 0x47445331
112 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
113 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
114 #define CFG_DDR_MODE 0x40020062 /* DLL,normal,seq,4/2.5 */
115 #define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */
120 * Flash on the Local Bus
122 #define CFG_LBC_FLASH_BASE 0xfe000000 /* Localbus SDRAM */
123 #define CFG_LBC_FLASH_SIZE 32 /* LBC SDRAM is 32MB */
125 #define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH 32M */
126 #define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
128 #define CFG_OR0_PRELIM 0xfe000040 /* 32MB Flash */
129 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
130 #define CFG_MAX_FLASH_SECT 256 /* sectors per device */
131 #undef CFG_FLASH_CHECKSUM
132 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
133 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
135 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
137 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
143 #define CFG_FLASH_CFI_DRIVER
144 #define CFG_FLASH_CFI
145 #define CFG_FLASH_EMPTY_INFO
147 #undef CONFIG_CLOCKS_IN_MHZ
150 #define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
151 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */
152 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
153 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
158 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
159 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
160 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
161 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
162 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
163 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
164 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
165 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
166 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
167 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
168 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
169 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
170 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
171 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
172 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
174 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
175 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
176 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
177 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
178 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
179 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
180 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
181 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
183 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
184 | CFG_LBC_LSDMR_RFCR5 \
185 | CFG_LBC_LSDMR_PRETOACT3 \
186 | CFG_LBC_LSDMR_ACTTORW3 \
187 | CFG_LBC_LSDMR_BL8 \
188 | CFG_LBC_LSDMR_WRC2 \
189 | CFG_LBC_LSDMR_CL3 \
190 | CFG_LBC_LSDMR_RFEN \
194 * SDRAM Controller configuration sequence.
196 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
197 | CFG_LBC_LSDMR_OP_PCHALL)
198 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
199 | CFG_LBC_LSDMR_OP_ARFRSH)
200 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
201 | CFG_LBC_LSDMR_OP_ARFRSH)
202 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
203 | CFG_LBC_LSDMR_OP_MRW)
204 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
205 | CFG_LBC_LSDMR_OP_NORMAL)
207 #define CONFIG_L1_INIT_RAM
208 #define CFG_INIT_RAM_LOCK 1
209 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
210 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
212 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
213 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
214 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
216 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
217 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
220 #define CONFIG_CONS_INDEX 1
221 #undef CONFIG_SERIAL_SOFTWARE_FIFO
223 #define CFG_NS16550_SERIAL
224 #define CFG_NS16550_REG_SIZE 1
225 #define CFG_NS16550_CLK get_bus_freq(0)
227 #define CFG_BAUDRATE_TABLE \
228 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
230 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
231 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
233 /* Use the HUSH parser */
234 #define CFG_HUSH_PARSER
235 #ifdef CFG_HUSH_PARSER
236 #define CFG_PROMPT_HUSH_PS2 "> "
240 #define CONFIG_HARD_I2C /* I2C with hardware support*/
241 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
242 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
243 #define CFG_I2C_SLAVE 0x7F
244 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
247 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
248 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
249 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
253 * Addresses are mapped 1-1.
255 #define CFG_PCI1_MEM_BASE 0x80000000
256 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
257 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
258 #define CFG_PCI1_IO_BASE 0xe2000000
259 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
260 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
262 #if defined(CONFIG_PCI)
264 #define CONFIG_NET_MULTI
265 #define CONFIG_PCI_PNP /* do pci plug-and-play */
267 #undef CONFIG_EEPRO100
270 #if !defined(CONFIG_PCI_PNP)
271 #define PCI_ENET0_IOADDR 0xe0000000
272 #define PCI_ENET0_MEMADDR 0xe0000000
273 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
276 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
277 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
279 #endif /* CONFIG_PCI */
282 #if defined(CONFIG_TSEC_ENET)
284 #ifndef CONFIG_NET_MULTI
285 #define CONFIG_NET_MULTI 1
288 #define CONFIG_MII 1 /* MII PHY management */
289 #undef CONFIG_MPC85XX_TSEC1
290 #define CONFIG_MPC85XX_TSEC2 1
291 #define TSEC1_PHY_ADDR 0
292 #define TSEC2_PHY_ADDR 1
293 #define TSEC1_PHYIDX 0
294 #define TSEC2_PHYIDX 0
296 #undef CONFIG_MPC85XX_FEC
297 #define FEC_PHY_ADDR 0
300 #define CONFIG_ETHPRIME "ENET1"
302 #endif /* CONFIG_TSEC_ENET */
309 #define CFG_ENV_IS_IN_FLASH 1
310 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
311 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
312 #define CFG_ENV_SIZE 0x2000
313 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE)
314 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
316 #define CFG_NO_FLASH 1 /* Flash is not usable now */
317 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
318 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
319 #define CFG_ENV_SIZE 0x2000
322 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
323 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
325 #if defined(CFG_RAMBOOT)
326 #if defined(CONFIG_PCI)
327 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
335 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
343 #if defined(CONFIG_PCI)
344 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
349 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
355 #include <cmd_confdefs.h>
357 #undef CONFIG_WATCHDOG /* watchdog disabled */
360 * Miscellaneous configurable options
362 #define CFG_LONGHELP /* undef to save memory */
363 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
364 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
366 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
367 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
369 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
372 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
373 #define CFG_MAXARGS 16 /* max number of command args */
374 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
375 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
378 * For booting Linux, the board info and command line data
379 * have to be in the first 8 MB of memory, since this is
380 * the maximum mapped by the Linux kernel during initialization.
382 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
384 /* Cache Configuration */
385 #define CFG_DCACHE_SIZE 32768
386 #define CFG_CACHELINE_SIZE 32
387 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
388 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
392 * Internal Definitions
396 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
397 #define BOOTFLAG_WARM 0x02 /* Software reboot */
399 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
400 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
401 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
405 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
407 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
409 #define CONFIG_BAUDRATE 115200
411 #define CONFIG_PREBOOT "echo;" \
412 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
415 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
417 #define CONFIG_EXTRA_ENV_SETTINGS \
420 "nfsargs=setenv bootargs root=/dev/nfs rw " \
421 "nfsroot=$serverip:$rootpath\0" \
422 "ramargs=setenv bootargs root=/dev/ram rw\0" \
423 "addip=setenv bootargs $bootargs " \
424 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
425 ":$hostname:$netdev:off panic=1\0" \
426 "addcons=setenv bootargs $bootargs " \
427 "console=$consdev,$baudrate\0" \
428 "flash_nfs=run nfsargs addip addcons;" \
429 "bootm $kernel_addr\0" \
430 "flash_self=run ramargs addip addcons;" \
431 "bootm $kernel_addr $ramdisk_addr\0" \
432 "net_nfs=tftp $loadaddr $bootfile;" \
433 "run nfsargs addip addcons;bootm\0" \
434 "rootpath=/opt/eldk/ppc_85xx\0" \
435 "bootfile=/tftpboot/tqm8540/uImage\0" \
436 "kernel_addr=FE000000\0" \
437 "ramdisk_addr=FE100000\0" \
439 #define CONFIG_BOOTCOMMAND "run flash_self"
441 #endif /* __CONFIG_H */