3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /************************************************************************
25 * acadia.h - configuration for AMCC Acadia (405EZ)
26 ***********************************************************************/
31 /*-----------------------------------------------------------------------
32 * High Level Configuration Options
33 *----------------------------------------------------------------------*/
34 #define CONFIG_ACADIA 1 /* Board is Acadia */
35 #define CONFIG_4xx 1 /* ... PPC4xx family */
36 #define CONFIG_405EZ 1 /* Specifc 405EZ support*/
39 * Include common defines/options for all AMCC eval boards
41 #define CONFIG_HOSTNAME acadia
42 #include "amcc-common.h"
44 /* Detect Acadia PLL input clock automatically via CPLD bit */
45 #define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \
48 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
49 #define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
51 #define CONFIG_NO_SERIAL_EEPROM
52 /*#undef CONFIG_NO_SERIAL_EEPROM*/
54 #ifdef CONFIG_NO_SERIAL_EEPROM
55 /*----------------------------------------------------------------------------
56 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
57 * assuming a 66MHz input clock to the 405EZ.
58 *---------------------------------------------------------------------------*/
59 /* #define PLLMR0_100_100_12 */
60 #define PLLMR0_200_133_66
61 /* #define PLLMR0_266_160_80 */
62 /* #define PLLMR0_333_166_83 */
65 /*-----------------------------------------------------------------------
66 * Base addresses -- Note these are effective addresses where the
67 * actual resources get mapped (not physical addresses)
68 *----------------------------------------------------------------------*/
69 #define CONFIG_SYS_FLASH_BASE 0xfe000000
70 #define CONFIG_SYS_CPLD_BASE 0x80000000
71 #define CONFIG_SYS_NAND_ADDR 0xd0000000
72 #define CONFIG_SYS_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
74 /*-----------------------------------------------------------------------
75 * Initial RAM & stack pointer
76 *----------------------------------------------------------------------*/
77 #define CONFIG_SYS_TEMP_STACK_OCM 1 /* OCM as init ram */
79 /* On Chip Memory location */
80 #define CONFIG_SYS_OCM_DATA_ADDR 0xf8000000
81 #define CONFIG_SYS_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
82 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SRAM */
83 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
85 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size for initial data */
86 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
87 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
89 /*-----------------------------------------------------------------------
91 *----------------------------------------------------------------------*/
92 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
93 #define CONFIG_SYS_BASE_BAUD 691200
95 /*-----------------------------------------------------------------------
97 *----------------------------------------------------------------------*/
98 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
99 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
101 #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
102 #define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
105 /*-----------------------------------------------------------------------
107 *----------------------------------------------------------------------*/
108 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
109 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
110 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
112 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
113 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
114 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
116 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
117 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
119 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
120 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
123 #define CONFIG_SYS_NO_FLASH 1 /* No NOR on Acadia when NAND-booting */
126 #ifdef CONFIG_ENV_IS_IN_FLASH
127 #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
128 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
129 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
131 /* Address and size of Redundant Environment Sector */
132 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
133 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
137 * IPL (Initial Program Loader, integrated inside CPU)
138 * Will load first 4k from NAND (SPL) into cache and execute it from there.
140 * SPL (Secondary Program Loader)
141 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
142 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
143 * controller and the NAND controller so that the special U-Boot image can be
144 * loaded from NAND to SDRAM.
147 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
148 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
150 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
151 * set up. While still running from cache, I experienced problems accessing
152 * the NAND controller. sr - 2006-08-25
154 #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
155 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
156 #define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
157 #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
158 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
159 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
162 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
164 #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
165 #define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
168 * Now the NAND chip has to be defined (no autodetection used!)
170 #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
171 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
172 #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
173 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
174 #undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
176 #define CONFIG_SYS_NAND_ECCSIZE 256
177 #define CONFIG_SYS_NAND_ECCBYTES 3
178 #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
179 #define CONFIG_SYS_NAND_OOBSIZE 16
180 #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
181 #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
183 #ifdef CONFIG_ENV_IS_IN_NAND
185 * For NAND booting the environment is embedded in the U-Boot image. Please take
186 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
188 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
189 #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
190 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
193 /*-----------------------------------------------------------------------
195 *----------------------------------------------------------------------*/
196 #define CONFIG_SYS_MBYTES_RAM 64 /* 64MB */
198 /*-----------------------------------------------------------------------
200 *----------------------------------------------------------------------*/
201 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
203 #define CONFIG_SYS_I2C_MULTI_EEPROMS
204 #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
205 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
206 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
207 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
209 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
210 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
211 #define CONFIG_DTT_AD7414 1 /* use AD7414 */
212 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
213 #define CONFIG_SYS_DTT_MAX_TEMP 70
214 #define CONFIG_SYS_DTT_LOW_TEMP -30
215 #define CONFIG_SYS_DTT_HYSTERESIS 3
217 /*-----------------------------------------------------------------------
219 *----------------------------------------------------------------------*/
220 #define CONFIG_PHY_ADDR 0 /* PHY address */
221 #define CONFIG_HAS_ETH0 1
224 * Default environment variables
226 #define CONFIG_EXTRA_ENV_SETTINGS \
227 CONFIG_AMCC_DEF_ENV \
228 CONFIG_AMCC_DEF_ENV_PPC \
229 CONFIG_AMCC_DEF_ENV_NOR_UPD \
230 CONFIG_AMCC_DEF_ENV_NAND_UPD \
231 "kernel_addr=fff10000\0" \
232 "ramdisk_addr=fff20000\0" \
233 "kozio=bootm ffc60000\0" \
236 #define CONFIG_USB_OHCI
237 #define CONFIG_USB_STORAGE
240 #define CONFIG_MAC_PARTITION
241 #define CONFIG_DOS_PARTITION
242 #define CONFIG_ISO_PARTITION
244 #define CONFIG_SUPPORT_VFAT
247 * Commands additional to the ones defined in amcc-common.h
249 #define CONFIG_CMD_DTT
250 #define CONFIG_CMD_NAND
251 #define CONFIG_CMD_USB
254 * No NOR on Acadia when NAND-booting
256 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
257 #undef CONFIG_CMD_FLASH
258 #undef CONFIG_CMD_IMLS
261 /*-----------------------------------------------------------------------
263 *----------------------------------------------------------------------*/
264 #define CONFIG_SYS_MAX_NAND_DEVICE 1
265 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
266 #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
268 /*-----------------------------------------------------------------------
269 * External Bus Controller (EBC) Setup
270 *----------------------------------------------------------------------*/
271 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
272 #define CONFIG_SYS_NAND_CS 3
273 /* Memory Bank 0 (Flash) initialization */
274 #define CONFIG_SYS_EBC_PB0AP 0x03337200
275 #define CONFIG_SYS_EBC_PB0CR 0xfe0bc000
277 /* Memory Bank 3 (NAND-FLASH) initialization */
278 #define CONFIG_SYS_EBC_PB3AP 0x018003c0
279 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
281 /* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
282 /* Memory Bank 1 (CRAM) initialization */
283 #define CONFIG_SYS_EBC_PB1AP 0x030400c0
284 #define CONFIG_SYS_EBC_PB1CR 0x000bc000
286 /* Memory Bank 2 (CRAM) initialization */
287 #define CONFIG_SYS_EBC_PB2AP 0x030400c0
288 #define CONFIG_SYS_EBC_PB2CR 0x020bc000
290 #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
291 /* Memory Bank 0 (NAND-FLASH) initialization */
292 #define CONFIG_SYS_EBC_PB0AP 0x018003c0
293 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
296 * When NAND-booting the CRAM EBC setup must be done in sync mode, since the
297 * NAND-SPL already initialized the CRAM and EBC to sync mode.
299 /* Memory Bank 1 (CRAM) initialization */
300 #define CONFIG_SYS_EBC_PB1AP 0x9C0201C0
301 #define CONFIG_SYS_EBC_PB1CR 0x000bc000
303 /* Memory Bank 2 (CRAM) initialization */
304 #define CONFIG_SYS_EBC_PB2AP 0x9C0201C0
305 #define CONFIG_SYS_EBC_PB2CR 0x020bc000
308 /* Memory Bank 4 (CPLD) initialization */
309 #define CONFIG_SYS_EBC_PB4AP 0x04006000
310 #define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CPLD_BASE | 0x18000)
312 #define CONFIG_SYS_EBC_CFG 0xf8400000
314 /*-----------------------------------------------------------------------
316 *----------------------------------------------------------------------*/
317 #define CONFIG_SYS_GPIO_CRAM_CLK 8
318 #define CONFIG_SYS_GPIO_CRAM_WAIT 9 /* GPIO-In */
319 #define CONFIG_SYS_GPIO_CRAM_ADV 10
320 #define CONFIG_SYS_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */
322 /*-----------------------------------------------------------------------
323 * Definitions for GPIO_0 setup (PPC405EZ specific)
325 * GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs
326 * GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output
327 * GPIO0[4] - External Bus Controller Hold Input
328 * GPIO0[5] - External Bus Controller Priority Input
329 * GPIO0[6] - External Bus Controller HLDA Output
330 * GPIO0[7] - External Bus Controller Bus Request Output
331 * GPIO0[8] - CRAM Clk Output
332 * GPIO0[9] - External Bus Controller Ready Input
333 * GPIO0[10] - CRAM Adv Output
334 * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
335 * GPIO0[25] - External DMA Request Input
336 * GPIO0[26] - External DMA EOT I/O
337 * GPIO0[25] - External DMA Ack_n Output
338 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
339 * GPIO0[28-30] - Trace Outputs / PWM Inputs
340 * GPIO0[31] - PWM_8 I/O
342 #define CONFIG_SYS_GPIO0_TCR 0xC0A00000
343 #define CONFIG_SYS_GPIO0_OSRL 0x50004400
344 #define CONFIG_SYS_GPIO0_OSRH 0x02000055
345 #define CONFIG_SYS_GPIO0_ISR1L 0x00001000
346 #define CONFIG_SYS_GPIO0_ISR1H 0x00000055
347 #define CONFIG_SYS_GPIO0_TSRL 0x02000000
348 #define CONFIG_SYS_GPIO0_TSRH 0x00000055
350 /*-----------------------------------------------------------------------
351 * Definitions for GPIO_1 setup (PPC405EZ specific)
353 * GPIO1[0-6] - PWM_9 to PWM_15 I/O
354 * GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input
355 * GPIO1[8] - TS5 Output / DAC_IP_TRIG Input
356 * GPIO1[9] - TS6 Output / ADC_IP_TRIG Input
357 * GPIO1[10-12] - UART0 Control Inputs
358 * GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
359 * GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output
360 * GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input
361 * GPIO1[16] - SPI_SS_1_N Output
362 * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
364 #define CONFIG_SYS_GPIO1_TCR 0xFFFF8414
365 #define CONFIG_SYS_GPIO1_OSRL 0x40000110
366 #define CONFIG_SYS_GPIO1_OSRH 0x55455555
367 #define CONFIG_SYS_GPIO1_ISR1L 0x15555445
368 #define CONFIG_SYS_GPIO1_ISR1H 0x00000000
369 #define CONFIG_SYS_GPIO1_TSRL 0x00000000
370 #define CONFIG_SYS_GPIO1_TSRH 0x00000000
372 #endif /* __CONFIG_H */