2 * (C) Copyright 2006-2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /*-----------------------------------------------------------------------
28 * High Level Configuration Options
29 *----------------------------------------------------------------------*/
30 #define CONFIG_ALPR 1 /* Board is ebony */
31 #define CONFIG_440GX 1 /* Specifc GX support */
32 #define CONFIG_440 1 /* ... PPC440 family */
33 #define CONFIG_4xx 1 /* ... PPC4xx family */
34 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
35 #define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
36 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
37 #define CONFIG_4xx_DCACHE /* Enable i- and d-cache */
39 /*-----------------------------------------------------------------------
40 * Base addresses -- Note these are effective addresses where the
41 * actual resources get mapped (not physical addresses)
42 *----------------------------------------------------------------------*/
43 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
44 #define CONFIG_SYS_FLASH_BASE 0xffe00000 /* start of FLASH */
45 #define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
46 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
47 #define CONFIG_SYS_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
48 #define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
49 #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
50 #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
51 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
52 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
53 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
56 #define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
57 #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
59 /*-----------------------------------------------------------------------
60 * Initial RAM & stack pointer (placed in internal SRAM)
61 *----------------------------------------------------------------------*/
62 #define CONFIG_SYS_TEMP_STACK_OCM 1
63 #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
64 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
65 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
66 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
68 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
69 #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
70 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
72 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
73 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
75 /*-----------------------------------------------------------------------
77 *----------------------------------------------------------------------*/
78 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
79 #define CONFIG_BAUDRATE 115200
80 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */
82 #define CONFIG_SYS_BAUDRATE_TABLE \
83 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
85 /*-----------------------------------------------------------------------
87 *----------------------------------------------------------------------*/
88 #define CONFIG_SYS_FLASH_CFI 1 /* The flash is CFI compatible */
89 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
90 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
91 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
92 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
93 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
94 #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
96 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
98 #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
99 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
100 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
102 /* Address and size of Redundant Environment Sector */
103 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
104 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
106 /*-----------------------------------------------------------------------
108 *----------------------------------------------------------------------*/
109 #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
110 #define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
111 #undef CONFIG_SDRAM_ECC /* enable ECC support */
112 #define CONFIG_SYS_SDRAM_TABLE { \
113 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
114 {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
116 /*-----------------------------------------------------------------------
118 *----------------------------------------------------------------------*/
119 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
120 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
121 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
122 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
123 #define CONFIG_SYS_I2C_SLAVE 0x7F
124 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
126 /*-----------------------------------------------------------------------
127 * I2C EEPROM (PCF8594C)
128 *----------------------------------------------------------------------*/
129 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
130 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
131 /* mask of address bits that overflow into the "EEPROM chip address" */
132 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
133 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
134 /* 8 byte page write mode using */
135 /* last 3 bits of the address */
136 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
138 #define CONFIG_PREBOOT "echo;" \
139 "echo Type \"run kernelx\" to boot the system;" \
142 #undef CONFIG_BOOTARGS
144 #define CONFIG_EXTRA_ENV_SETTINGS \
147 "fdt_file=alpr/alpr.dtb\0" \
148 "fdt_addr=400000\0" \
149 "nfsargs=setenv bootargs root=/dev/nfs rw " \
150 "nfsroot=${serverip}:${rootpath} ${init}\0" \
151 "ramargs=setenv bootargs root=/dev/ram rw\0" \
152 "addip=setenv bootargs ${bootargs} " \
153 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
154 ":${hostname}:${netdev}:off panic=1\0" \
155 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
157 "flash_nfs=run nfsargs addip addtty;" \
158 "bootm ${kernel_addr}\0" \
159 "flash_self=run ramargs addip addtty;" \
160 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
161 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
163 "net_nfs_fdt=tftp 200000 ${bootfile};" \
164 "tftp ${fdt_addr} ${fdt_file};" \
165 "run nfsargs addip addtty;" \
166 "bootm 200000 - ${fdt_addr}\0" \
167 "rootpath=/opt/projects/alpr/nfs_root\0" \
168 "bootfile=/alpr/uImage\0" \
169 "kernel_addr=fff00000\0" \
170 "ramdisk_addr=fff10000\0" \
171 "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \
172 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
173 "cp.b 100000 fffc0000 40000;" \
174 "setenv filesize;saveenv\0" \
175 "upd=run load update\0" \
176 "ethprime=ppc_4xx_eth3\0" \
177 "ethact=ppc_4xx_eth3\0" \
179 "ipconfig=dhcp;setenv serverip 11.0.0.152\0" \
180 "load_fpga=fpga load 0 ffe00000 10dd9a\0" \
181 "mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \
182 "rootfstype=jffs2 init=/sbin/init\0" \
183 "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
185 "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
186 "addtty;bootm 200000\0" \
187 "kernel1=setenv actkernel 'kernel1';run load_fpga " \
189 "kernel2=setenv actkernel 'kernel2';run load_fpga " \
193 #define CONFIG_BOOTCOMMAND "run kernel2"
195 #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
197 #define CONFIG_BAUDRATE 115200
199 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
200 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
202 #define CONFIG_PPC4xx_EMAC
203 #define CONFIG_MII 1 /* MII PHY management */
204 #define CONFIG_NET_MULTI 1
205 #define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */
206 #define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */
207 #define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */
208 #define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */
209 #define CONFIG_HAS_ETH0
210 #define CONFIG_HAS_ETH1
211 #define CONFIG_HAS_ETH2
212 #define CONFIG_HAS_ETH3
213 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
214 #define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/
215 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
216 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
218 #define CONFIG_NETCONSOLE /* include NetConsole support */
224 #define CONFIG_BOOTP_BOOTFILESIZE
225 #define CONFIG_BOOTP_BOOTPATH
226 #define CONFIG_BOOTP_GATEWAY
227 #define CONFIG_BOOTP_HOSTNAME
231 * Command line configuration.
233 #include <config_cmd_default.h>
235 #define CONFIG_CMD_DHCP
236 #define CONFIG_CMD_EEPROM
237 #define CONFIG_CMD_FPGA
238 #define CONFIG_CMD_I2C
239 #undef CONFIG_CMD_LOADB
240 #undef CONFIG_CMD_LOADS
241 #define CONFIG_CMD_MII
242 #define CONFIG_CMD_NAND
243 #define CONFIG_CMD_NET
244 #undef CONFIG_CMD_NFS
245 #define CONFIG_CMD_PCI
247 #undef CONFIG_WATCHDOG /* watchdog disabled */
250 * Miscellaneous configurable options
252 #define CONFIG_SYS_LONGHELP /* undef to save memory */
253 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
254 #if defined(CONFIG_CMD_KGDB)
255 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
257 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
259 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
260 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
261 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
263 #define CONFIG_SYS_ALT_MEMTEST 1 /* Enable more extensive memtest*/
264 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
265 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
267 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
268 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
270 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
272 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
273 #define CONFIG_LOOPW 1 /* enable loopw command */
274 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
275 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
276 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
278 #define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
280 /*-----------------------------------------------------------------------
282 *-----------------------------------------------------------------------
285 #define CONFIG_PCI /* include pci support */
286 #define CONFIG_PCI_PNP /* do pci plug-and-play */
287 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
288 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
289 #define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
291 /* Board-specific PCI */
292 #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
293 #define CONFIG_SYS_PCI_MASTER_INIT
295 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
296 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
298 /*-----------------------------------------------------------------------
300 *-----------------------------------------------------------------------*/
302 #define CONFIG_FPGA_ALTERA
303 #define CONFIG_FPGA_CYCLON2
304 #define CONFIG_SYS_FPGA_CHECK_CTRLC
305 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
306 #define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
307 Reihe geschaltet -> sollte gehen,
308 aufpassen mit Datasize ist jetzt
309 halt doppelt so gross ... Seite 306
310 ist das mit den multiple Device in PS
313 /* FPGA program pin configuration */
314 #define CONFIG_SYS_GPIO_CLK 18 /* FPGA clk pin (cpu output) */
315 #define CONFIG_SYS_GPIO_DATA 19 /* FPGA data pin (cpu output) */
316 #define CONFIG_SYS_GPIO_STATUS 20 /* FPGA status pin (cpu input) */
317 #define CONFIG_SYS_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */
318 #define CONFIG_SYS_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */
320 #define CONFIG_SYS_GPIO_SEL_DPR 14 /* cpu output */
321 #define CONFIG_SYS_GPIO_SEL_AVR 15 /* cpu output */
322 #define CONFIG_SYS_GPIO_PROG_EN 23 /* cpu output */
324 /*-----------------------------------------------------------------------
325 * Definitions for GPIO setup
326 *-----------------------------------------------------------------------*/
327 #define CONFIG_SYS_GPIO_SHUTDOWN (0x80000000 >> 6)
328 #define CONFIG_SYS_GPIO_SSD_EMPTY (0x80000000 >> 9)
329 #define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 26)
330 #define CONFIG_SYS_GPIO_REV0 (0x80000000 >> 14)
331 #define CONFIG_SYS_GPIO_REV1 (0x80000000 >> 15)
333 /*-----------------------------------------------------------------------
335 *-----------------------------------------------------------------------*/
336 #define CONFIG_SYS_MAX_NAND_DEVICE 4
337 #define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */
338 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \
339 CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
340 #define CONFIG_SYS_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */
342 /*-----------------------------------------------------------------------
343 * External Bus Controller (EBC) Setup
344 *----------------------------------------------------------------------*/
345 #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
347 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
348 #define CONFIG_SYS_EBC_PB0AP 0x92015480
349 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
351 /* Memory Bank 1 (NAND-FLASH) initialization */
352 #define CONFIG_SYS_EBC_PB1AP 0x01840380 /* TWT=3 */
353 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
356 * For booting Linux, the board info and command line data
357 * have to be in the first 8 MB of memory, since this is
358 * the maximum mapped by the Linux kernel during initialization.
360 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
363 * Internal Definitions
367 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
368 #define BOOTFLAG_WARM 0x02 /* Software reboot */
370 #if defined(CONFIG_CMD_KGDB)
371 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
372 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
375 /* pass open firmware flat tree */
376 #define CONFIG_OF_LIBFDT 1
377 #define CONFIG_OF_BOARD_SETUP 1
379 #endif /* __CONFIG_H */