2 * (C) Copyright 2005-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /************************************************************************
25 * bamboo.h - configuration for BAMBOO board
26 ***********************************************************************/
30 /*-----------------------------------------------------------------------
31 * High Level Configuration Options
32 *----------------------------------------------------------------------*/
33 #define CONFIG_BAMBOO 1 /* Board is BAMBOO */
34 #define CONFIG_440EP 1 /* Specific PPC440EP support */
35 #define CONFIG_440 1 /* ... PPC440 family */
36 #define CONFIG_4xx 1 /* ... PPC4xx family */
37 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
40 * Include common defines/options for all AMCC eval boards
42 #define CONFIG_HOSTNAME bamboo
43 #include "amcc-common.h"
45 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
48 * Please note that, if NAND support is enabled, the 2nd ethernet port
49 * can't be used because of pin multiplexing. So, if you want to use the
50 * 2nd ethernet port you have to "undef" the following define.
52 #define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
54 /*-----------------------------------------------------------------------
55 * Base addresses -- Note these are effective addresses where the
56 * actual resources get mapped (not physical addresses)
57 *----------------------------------------------------------------------*/
58 #define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
59 #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
60 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
61 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
62 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
64 /*Don't change either of these*/
65 #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
66 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
67 /*Don't change either of these*/
69 #define CONFIG_SYS_USB_DEVICE 0x50000000
70 #define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000
71 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
72 #define CONFIG_SYS_NAND_ADDR 0x90000000
73 #define CONFIG_SYS_NAND2_ADDR 0x94000000
75 /*-----------------------------------------------------------------------
76 * Initial RAM & stack pointer (placed in SDRAM)
77 *----------------------------------------------------------------------*/
78 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
79 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
80 #define CONFIG_SYS_INIT_RAM_END (4 << 10)
81 #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
82 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
83 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
85 /*-----------------------------------------------------------------------
87 *----------------------------------------------------------------------*/
88 #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
89 /* define this if you want console on UART1 */
90 #undef CONFIG_UART1_CONSOLE
92 /*-----------------------------------------------------------------------
95 * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
96 * The DS1558 code assumes this condition
98 *----------------------------------------------------------------------*/
99 #define CONFIG_SYS_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
100 #define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
102 /*-----------------------------------------------------------------------
104 *----------------------------------------------------------------------*/
105 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
106 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
108 #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
109 #define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
112 /*-----------------------------------------------------------------------
114 *----------------------------------------------------------------------*/
115 #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
116 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
118 #undef CONFIG_SYS_FLASH_CHECKSUM
119 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
120 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
122 #define CONFIG_SYS_FLASH_ADDR0 0x555
123 #define CONFIG_SYS_FLASH_ADDR1 0x2aa
124 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
126 #define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
127 #define CONFIG_SYS_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
129 #ifdef CONFIG_ENV_IS_IN_FLASH
130 #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
131 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
132 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
134 /* Address and size of Redundant Environment Sector */
135 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
136 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
137 #endif /* CONFIG_ENV_IS_IN_FLASH */
140 * IPL (Initial Program Loader, integrated inside CPU)
141 * Will load first 4k from NAND (SPL) into cache and execute it from there.
143 * SPL (Secondary Program Loader)
144 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
145 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
146 * controller and the NAND controller so that the special U-Boot image can be
147 * loaded from NAND to SDRAM.
150 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
151 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
153 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
154 * set up. While still running from cache, I experienced problems accessing
155 * the NAND controller. sr - 2006-08-25
157 #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
158 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
159 #define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
160 #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
161 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
162 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
165 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
167 #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
168 #define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
171 * Now the NAND chip has to be defined (no autodetection used!)
173 #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
174 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
175 #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
176 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
177 #define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
179 #define CONFIG_SYS_NAND_ECCSIZE 256
180 #define CONFIG_SYS_NAND_ECCBYTES 3
181 #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
182 #define CONFIG_SYS_NAND_OOBSIZE 16
183 #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
184 #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
186 #ifdef CONFIG_ENV_IS_IN_NAND
188 * For NAND booting the environment is embedded in the U-Boot image. Please take
189 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
191 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
192 #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
193 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
196 /*-----------------------------------------------------------------------
198 *----------------------------------------------------------------------*/
199 #define CONFIG_SYS_MAX_NAND_DEVICE 2
200 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
201 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
202 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
203 #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
205 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
206 #define CONFIG_SYS_NAND_CS 1
208 #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
209 /* Memory Bank 0 (NAND-FLASH) initialization */
210 #define CONFIG_SYS_EBC_PB0AP 0x018003c0
211 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
214 /*-----------------------------------------------------------------------
216 *----------------------------------------------------------------------------- */
217 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
218 #undef CONFIG_DDR_ECC /* don't use ECC */
219 #define CONFIG_SYS_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
220 #define SPD_EEPROM_ADDRESS {CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51}
221 #define CONFIG_SYS_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
222 #define CONFIG_PROG_SDRAM_TLB
224 /*-----------------------------------------------------------------------
226 *----------------------------------------------------------------------*/
227 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
229 #define CONFIG_SYS_I2C_MULTI_EEPROMS
230 #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
231 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
235 #ifdef CONFIG_ENV_IS_IN_EEPROM
236 #define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
237 #define CONFIG_ENV_OFFSET 0x0
238 #endif /* CONFIG_ENV_IS_IN_EEPROM */
241 * Default environment variables
243 #define CONFIG_EXTRA_ENV_SETTINGS \
244 CONFIG_AMCC_DEF_ENV \
245 CONFIG_AMCC_DEF_ENV_POWERPC \
246 CONFIG_AMCC_DEF_ENV_PPC_OLD \
247 CONFIG_AMCC_DEF_ENV_NOR_UPD \
248 CONFIG_AMCC_DEF_ENV_NAND_UPD \
249 "kernel_addr=fff00000\0" \
250 "ramdisk_addr=fff10000\0" \
253 #define CONFIG_HAS_ETH0
254 #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
255 #define CONFIG_PHY1_ADDR 1
257 #ifndef CONFIG_BAMBOO_NAND
258 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
259 #endif /* CONFIG_BAMBOO_NAND */
263 #define CONFIG_USB_OHCI
264 #define CONFIG_USB_STORAGE
266 /*Comment this out to enable USB 1.1 device*/
267 #define USB_2_0_DEVICE
268 #endif /*CONFIG_440EP*/
271 * Commands additional to the ones defined in amcc-common.h
273 #define CONFIG_CMD_DATE
274 #define CONFIG_CMD_EXT2
275 #define CONFIG_CMD_FAT
276 #define CONFIG_CMD_PCI
277 #define CONFIG_CMD_SDRAM
278 #define CONFIG_CMD_SNTP
279 #define CONFIG_CMD_USB
281 #ifdef CONFIG_BAMBOO_NAND
282 #define CONFIG_CMD_NAND
285 #define CONFIG_SUPPORT_VFAT
288 #define CONFIG_MAC_PARTITION
289 #define CONFIG_DOS_PARTITION
290 #define CONFIG_ISO_PARTITION
292 /*-----------------------------------------------------------------------
294 *-----------------------------------------------------------------------
297 #define CONFIG_PCI /* include pci support */
298 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
299 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
300 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
302 /* Board-specific PCI */
303 #define CONFIG_SYS_PCI_TARGET_INIT
304 #define CONFIG_SYS_PCI_MASTER_INIT
306 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
307 #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
309 #endif /* __CONFIG_H */