2 * U-boot - Configuration file for BF533 EZKIT board
5 #ifndef __CONFIG_EZKIT533_H__
6 #define __CONFIG_EZKIT533_H__
8 #include <asm/blackfin-config-pre.h>
10 #define CONFIG_BAUDRATE 57600
11 #define CONFIG_STAMP 1
13 #define CONFIG_BOOTDELAY 5
14 #define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
16 #define CFG_LONGHELP 1
17 #define CONFIG_CMDLINE_EDITING 1
18 #define CONFIG_LOADADDR 0x01000000 /* default load address */
19 #define CONFIG_BOOTCOMMAND "tftp $(loadaddr) linux"
20 /* #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" */
22 #define CONFIG_DRIVER_SMC91111 1
23 #define CONFIG_SMC91111_BASE 0x20310300
27 #define CFG_DISCOVER_PHY
30 #define CONFIG_RTC_BFIN 1
31 #define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
35 * Blackfin can support several boot modes
37 #define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
38 #define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
39 #define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
40 /* Define the boot mode */
41 #define BFIN_BOOT_MODE BF533_BYPASS_BOOT
42 /* #define BFIN_BOOT_MODE BF533_SPI_BOOT */
44 #define CONFIG_PANIC_HANG 1
46 #define CONFIG_BFIN_CPU bf533-0.3
48 /* This sets the default state of the cache on U-Boot's boot */
49 #define CONFIG_ICACHE_ON
50 #define CONFIG_DCACHE_ON
52 /* Define where the uboot will be loaded by on-chip boot rom */
53 #define APP_ENTRY 0x00001000
55 /* CONFIG_CLKIN_HZ is any value in Hz */
56 #define CONFIG_CLKIN_HZ 27000000
57 /* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
59 #define CONFIG_CLKIN_HALF 0
60 /* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
62 #define CONFIG_PLL_BYPASS 0
63 /* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
64 /* Values can range from 1-64 */
65 #define CONFIG_VCO_MULT 22
66 /* CONFIG_CCLK_DIV controls what the core clock divider is */
67 /* Values can be 1, 2, 4, or 8 ONLY */
68 #define CONFIG_CCLK_DIV 1
69 /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
70 /* Values can range from 1-15 */
71 #define CONFIG_SCLK_DIV 5
72 /* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
73 /* Values can range from 2-65535 */
74 /* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
75 #define CONFIG_SPI_BAUD 2
76 #define CONFIG_SPI_BAUD_INITBLOCK 4
78 #if ( CONFIG_CLKIN_HALF == 0 )
79 #define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
81 #define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
84 #if (CONFIG_PLL_BYPASS == 0)
85 #define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
86 #define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
88 #define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
89 #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
92 #define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */
93 #define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
94 #define CONFIG_MEM_MT48LC16M16A2TG_75 1
96 #define CONFIG_LOADS_ECHO 1
102 #define CONFIG_BOOTP_BOOTFILESIZE
103 #define CONFIG_BOOTP_BOOTPATH
104 #define CONFIG_BOOTP_GATEWAY
105 #define CONFIG_BOOTP_HOSTNAME
109 * Command line configuration.
111 #include <config_cmd_default.h>
113 #define CONFIG_CMD_PING
114 #define CONFIG_CMD_ELF
115 #define CONFIG_CMD_I2C
116 #define CONFIG_CMD_JFFS2
117 #define CONFIG_CMD_DATE
120 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
122 #define CFG_PROMPT "bfin> " /* Monitor Command Prompt */
123 #if defined(CONFIG_CMD_KGDB)
124 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
126 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
128 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
129 #define CFG_MAXARGS 16 /* max number of command args */
130 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
131 #define CFG_MEMTEST_START 0x00000000 /* memtest works on */
132 #define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024 * 1024) /* 1 ... 31 MB in DRAM */
133 #define CFG_LOAD_ADDR 0x01000000 /* default load address */
134 #define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */
135 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
136 #define CFG_SDRAM_BASE 0x00000000
137 #define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
138 #define CFG_FLASH_BASE 0x20000000
140 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
141 #define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
142 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
143 #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
144 #define CFG_GBL_DATA_SIZE 0x4000
145 #define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
146 #define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
148 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
149 #define CFG_FLASH0_BASE 0x20000000
150 #define CFG_FLASH1_BASE 0x20200000
151 #define CFG_FLASH2_BASE 0x20280000
152 #define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
153 #define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */
155 #define CFG_ENV_IS_IN_FLASH 1
156 #define CFG_ENV_ADDR 0x20020000
157 #define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
159 /* JFFS Partition offset set */
160 #define CFG_JFFS2_FIRST_BANK 0
161 #define CFG_JFFS2_NUM_BANKS 1
162 /* 512k reserved for u-boot */
163 #define CFG_JFFS2_FIRST_SECTOR 11
169 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
172 #define FLASH_TOT_SECT 40
173 #define FLASH_SIZE 0x220000
174 #define CFG_FLASH_SIZE 0x220000
177 * Initialize PSD4256 registers for using I2C
179 #define CONFIG_MISC_INIT_R
183 * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
185 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
187 * Software (bit-bang) I2C driver configuration
192 #define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
193 #define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
194 #define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
195 #define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
196 #define I2C_SDA(bit) if(bit) { \
197 *pFIO_FLAG_S = PF_SDA; \
201 *pFIO_FLAG_C = PF_SDA; \
204 #define I2C_SCL(bit) if(bit) { \
205 *pFIO_FLAG_S = PF_SCL; \
209 *pFIO_FLAG_C = PF_SCL; \
212 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
214 #define CFG_I2C_SPEED 50000
215 #define CFG_I2C_SLAVE 0xFE
217 #define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
219 /* 0xFF, 0x7BB07BB0, 0x22547BB0 */
220 /* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
221 #define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
222 ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
223 #define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
224 B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
226 #define AMGCTLVAL 0xFF
227 #define AMBCTL0VAL 0x7BB07BB0
228 #define AMBCTL1VAL 0xFFC27BB0
230 #define CONFIG_VDSP 1
233 #define ET_EXEC_VDSP 0x8
234 #define SHT_STRTAB_VDSP 0x1
235 #define ELFSHDRSIZE_VDSP 0x2C
236 #define VDSP_ENTRY_ADDR 0xFFA00000