3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jmonkman@adventnetworks.com>
14 * Advent Networks, Inc. <http://www.adventnetworks.com>
15 * Oliver Brown <obrown@adventnetworks.com>
17 * SPDX-License-Identifier: GPL-2.0+
20 /*********************************************************************/
22 * This file contains the board configuartion for the GW8260 board.
27 * RESTRICTIONS/LIMITATIONS:
30 * Copyright (c) 2001, Advent Networks, Inc.
32 /*********************************************************************/
37 #define CONFIG_SYS_TEXT_BASE 0x40000000
39 /* Enable debug prints */
40 #undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
42 /* What is the oscillator's (UX2) frequency in Hz? */
43 #define CONFIG_8260_CLKIN (66 * 1000 * 1000)
45 /*-----------------------------------------------------------------------
46 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
47 *-----------------------------------------------------------------------
48 * What should MODCK_H be? It is dependent on the oscillator
49 * frequency, MODCK[1-3], and desired CPM and core frequencies.
50 * Here are some example values (all frequencies are in MHz):
52 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
53 * ------- ---------- --- --- ---- ----- ----- -----
54 * 0x5 0x5 66 133 133 Open Close Open
55 * 0x5 0x6 66 133 166 Open Open Close
56 * 0x5 0x7 66 133 200 Open Open Open
57 * 0x6 0x0 66 133 233 Close Close Close
58 * 0x6 0x1 66 133 266 Close Close Open
59 * 0x6 0x2 66 133 300 Close Open Close
61 #define CONFIG_SYS_SBC_MODCK_H 0x05
63 /* Define this if you want to boot from 0x00000100. If you don't define
64 * this, you will need to program the bootloader to 0xfff00000, and
65 * get the hardware reset config words at 0xfe000000. The simplest
66 * way to do that is to program the bootloader at both addresses.
67 * It is suggested that you just let U-Boot live at 0x00000000.
69 #define CONFIG_SYS_SBC_BOOT_LOW 1
71 /* What should the base address of the main FLASH be and how big is
72 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE.
73 * The main FLASH is whichever is connected to *CS0. U-Boot expects
74 * this to be the SIMM.
76 #define CONFIG_SYS_FLASH0_BASE 0x40000000
77 #define CONFIG_SYS_FLASH0_SIZE 8
79 /* Define CONFIG_SYS_FLASH_CHECKSUM to enable flash checksum during boot.
80 * Note: the 'flashchecksum' environment variable must also be set to 'y'.
82 #define CONFIG_SYS_FLASH_CHECKSUM
84 /* What should be the base address of SDRAM DIMM and how big is
87 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
88 #define CONFIG_SYS_SDRAM0_SIZE 64
92 * CONFIG_SYS_DRAM_TEST - enables the following tests.
94 * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
95 * Environment variable 'test_dram_data' must be
97 * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
98 * addressable. Environment variable
99 * 'test_dram_address' must be set to 'y'.
100 * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
101 * This test takes about 6 minutes to test 64 MB.
102 * Environment variable 'test_dram_walk' must be
105 #define CONFIG_SYS_DRAM_TEST
106 #if defined(CONFIG_SYS_DRAM_TEST)
107 #define CONFIG_SYS_DRAM_TEST_DATA
108 #define CONFIG_SYS_DRAM_TEST_ADDRESS
109 #define CONFIG_SYS_DRAM_TEST_WALK
110 #endif /* CONFIG_SYS_DRAM_TEST */
113 * GW8260 with 16 MB DIMM:
115 * 0x0000 0000 Exception Vector code, 8k
118 * 0x0000 2000 Free for Application Use
124 * 0x00F5 FF30 Monitor Stack (Growing downward)
125 * Monitor Stack Buffer (0x80)
126 * 0x00F5 FFB0 Board Info Data
127 * 0x00F6 0000 Malloc Arena
128 * : CONFIG_ENV_SECT_SIZE, 256k
129 * : CONFIG_SYS_MALLOC_LEN, 128k
130 * 0x00FC 0000 RAM Copy of Monitor Code
131 * : CONFIG_SYS_MONITOR_LEN, 256k
132 * 0x00FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
136 * GW8260 with 64 MB DIMM:
138 * 0x0000 0000 Exception Vector code, 8k
141 * 0x0000 2000 Free for Application Use
147 * 0x03F5 FF30 Monitor Stack (Growing downward)
148 * Monitor Stack Buffer (0x80)
149 * 0x03F5 FFB0 Board Info Data
150 * 0x03F6 0000 Malloc Arena
151 * : CONFIG_ENV_SECT_SIZE, 256k
152 * : CONFIG_SYS_MALLOC_LEN, 128k
153 * 0x03FC 0000 RAM Copy of Monitor Code
154 * : CONFIG_SYS_MONITOR_LEN, 256k
155 * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
160 * select serial console configuration
162 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
163 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
166 * if CONFIG_CONS_NONE is defined, then the serial console routines must
169 #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
170 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
171 #undef CONFIG_CONS_NONE /* define if console on neither */
172 #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
175 * select ethernet configuration
177 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
178 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
181 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
182 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
185 #undef CONFIG_ETHER_ON_SCC
186 #define CONFIG_ETHER_ON_FCC
187 #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
189 #ifdef CONFIG_ETHER_ON_SCC
190 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
191 #endif /* CONFIG_ETHER_ON_SCC */
193 #ifdef CONFIG_ETHER_ON_FCC
194 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
195 #define CONFIG_MII /* MII PHY management */
196 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
198 * Port pins used for bit-banged MII communictions (if applicable).
200 #define MDIO_PORT 2 /* Port C */
202 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
203 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
204 #define MDC_DECLARE MDIO_DECLARE
206 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
207 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
208 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
210 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
211 else iop->pdat &= ~0x00400000
213 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
214 else iop->pdat &= ~0x00200000
216 #define MIIDELAY udelay(1)
217 #endif /* CONFIG_ETHER_ON_FCC */
219 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
224 * - Select bus for bd/buffers (see 28-13)
225 * - Enable Full Duplex in FSMR
227 # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
228 # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
229 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
230 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
232 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
237 * - Select bus for bd/buffers (see 28-13)
238 * - Enable Full Duplex in FSMR
240 # define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
241 # define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
242 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
243 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
245 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
247 /* Define this to reserve an entire FLASH sector (256 KB) for
248 * environment variables. Otherwise, the environment will be
249 * put in the same sector as U-Boot, and changing variables
250 * will erase U-Boot temporarily
252 #define CONFIG_ENV_IN_OWN_SECT
254 /* Define to allow the user to overwrite serial and ethaddr */
255 #define CONFIG_ENV_OVERWRITE
257 /* What should the console's baud rate be? */
258 #define CONFIG_BAUDRATE 115200
260 /* Ethernet MAC address - This is set to all zeros to force an
261 * an error if we use BOOTP without setting
264 #define CONFIG_ETHADDR 00:00:00:00:00:00
266 /* Set to a positive value to delay for running BOOTCOMMAND */
267 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
269 /* Be selective on what keys can delay or stop the autoboot process
272 #define CONFIG_AUTOBOOT_KEYED
273 #define CONFIG_AUTOBOOT_PROMPT \
274 "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
275 #define CONFIG_AUTOBOOT_STOP_STR " "
276 #undef CONFIG_AUTOBOOT_DELAY_STR
277 #define DEBUG_BOOTKEYS 0
282 #define CONFIG_BOOTP_SUBNETMASK
283 #define CONFIG_BOOTP_GATEWAY
284 #define CONFIG_BOOTP_HOSTNAME
285 #define CONFIG_BOOTP_BOOTPATH
287 #define CONFIG_BOOTP_BOOTFILESIZE
288 #define CONFIG_BOOTP_DNS
290 /* undef this to save memory */
291 #define CONFIG_SYS_LONGHELP
293 /* Monitor Command Prompt */
297 * Command line configuration.
299 #include <config_cmd_default.h>
301 #define CONFIG_CMD_BEDBUG
302 #define CONFIG_CMD_ELF
303 #define CONFIG_CMD_ASKENV
304 #define CONFIG_CMD_REGINFO
305 #define CONFIG_CMD_IMMAP
306 #define CONFIG_CMD_MII
308 #undef CONFIG_CMD_KGDB
311 /* Where do the internal registers live? */
312 #define CONFIG_SYS_IMMR 0xf0000000
314 /* Use the HUSH parser */
315 #define CONFIG_SYS_HUSH_PARSER
316 #ifdef CONFIG_SYS_HUSH_PARSER
319 /* What is the address of IO controller */
320 #define CONFIG_SYS_IO_BASE 0xe0000000
322 /*****************************************************************************
324 * You should not have to modify any of the following settings
326 *****************************************************************************/
328 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
329 #define CONFIG_GW8260 1 /* on an GW8260 Board */
330 #define CONFIG_CPM2 1 /* Has a CPM2 */
333 * Miscellaneous configurable options
335 #if defined(CONFIG_CMD_KGDB)
336 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
338 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
341 /* Print Buffer Size */
342 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
344 #define CONFIG_SYS_MAXARGS 8 /* max number of command args */
346 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
348 /* Convert clocks to MHZ when passing board info to kernel.
349 * This must be defined for eariler 2.4 kernels (~2.4.4).
351 #define CONFIG_CLOCKS_IN_MHZ
353 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
354 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
357 /* memtest works from the end of the exception vector table
358 * to the end of the DRAM less monitor and malloc area
360 #define CONFIG_SYS_MEMTEST_START 0x2000
362 #define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
364 #define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
365 + CONFIG_SYS_MALLOC_LEN \
366 + CONFIG_ENV_SECT_SIZE \
367 + CONFIG_SYS_STACK_USAGE )
369 #define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
370 - CONFIG_SYS_MEM_END_USAGE )
373 * Low Level Configuration Settings
374 * (address mappings, register initial values, etc.)
375 * You should know what you are doing if you make changes here.
378 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
379 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
380 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
381 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE
383 /*-----------------------------------------------------------------------
384 * Hard Reset Configuration Words
386 #if defined(CONFIG_SYS_SBC_BOOT_LOW)
387 # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
389 # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
390 #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
392 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
393 #define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
394 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
395 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
397 #define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS11 | \
399 CONFIG_SYS_SBC_HRCW_IMMR | \
404 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \
405 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
408 #define CONFIG_SYS_HRCW_SLAVE1 0
409 #define CONFIG_SYS_HRCW_SLAVE2 0
410 #define CONFIG_SYS_HRCW_SLAVE3 0
411 #define CONFIG_SYS_HRCW_SLAVE4 0
412 #define CONFIG_SYS_HRCW_SLAVE5 0
413 #define CONFIG_SYS_HRCW_SLAVE6 0
414 #define CONFIG_SYS_HRCW_SLAVE7 0
416 /*-----------------------------------------------------------------------
417 * Definitions for initial stack pointer and data area (in DPRAM)
419 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
420 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
421 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
422 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
424 /*-----------------------------------------------------------------------
425 * Start addresses for the final memory configuration
426 * (Set up by the startup code)
427 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
428 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
430 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
432 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
433 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
436 * For booting Linux, the board info and command line data
437 * have to be in the first 8 MB of memory, since this is
438 * the maximum mapped by the Linux kernel during initialization.
440 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* Initial Memory map for Linux */
442 /*-----------------------------------------------------------------------
443 * FLASH and environment organization
445 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
446 #define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
448 #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
449 #define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
451 #define CONFIG_ENV_IS_IN_FLASH 1
453 #ifdef CONFIG_ENV_IN_OWN_SECT
454 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + (256 * 1024))
455 # define CONFIG_ENV_SECT_SIZE (256 * 1024)
457 # define CONFIG_ENV_SIZE (16 * 1024)/* Size of Environment Sector */
458 # define CONFIG_ENV_ADD ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SIZE)
459 # define CONFIG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size */
460 #endif /* CONFIG_ENV_IN_OWN_SECT */
462 /*-----------------------------------------------------------------------
463 * Cache Configuration
465 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
467 #if defined(CONFIG_CMD_KGDB)
468 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
471 /*-----------------------------------------------------------------------
472 * HIDx - Hardware Implementation-dependent Registers 2-11
473 *-----------------------------------------------------------------------
474 * HID0 also contains cache control - initially enable both caches and
475 * invalidate contents, then the final state leaves only the instruction
476 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
477 * but Soft reset does not.
479 * HID1 has only read-only information - nothing to set.
481 #define CONFIG_SYS_HID0_INIT (HID0_ICE |\
488 #define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
492 #define CONFIG_SYS_HID2 0
494 /*-----------------------------------------------------------------------
495 * RMR - Reset Mode Register
496 *-----------------------------------------------------------------------
498 #define CONFIG_SYS_RMR 0
500 /*-----------------------------------------------------------------------
501 * BCR - Bus Configuration 4-25
502 *-----------------------------------------------------------------------
504 #define CONFIG_SYS_BCR (BCR_ETM)
506 /*-----------------------------------------------------------------------
507 * SIUMCR - SIU Module Configuration 4-31
508 *-----------------------------------------------------------------------
510 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\
516 /*-----------------------------------------------------------------------
517 * SYPCR - System Protection Control 11-9
518 * SYPCR can only be written once after reset!
519 *-----------------------------------------------------------------------
520 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
522 #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
529 /*-----------------------------------------------------------------------
530 * TMCNTSC - Time Counter Status and Control 4-40
531 *-----------------------------------------------------------------------
532 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
533 * and enable Time Counter
535 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
540 /*-----------------------------------------------------------------------
541 * PISCR - Periodic Interrupt Status and Control 4-42
542 *-----------------------------------------------------------------------
543 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
546 #define CONFIG_SYS_PISCR (PISCR_PS |\
550 /*-----------------------------------------------------------------------
551 * SCCR - System Clock Control 9-8
552 *-----------------------------------------------------------------------
554 #define CONFIG_SYS_SCCR 0
556 /*-----------------------------------------------------------------------
557 * RCCR - RISC Controller Configuration 13-7
558 *-----------------------------------------------------------------------
560 #define CONFIG_SYS_RCCR 0
563 * Initialize Memory Controller:
565 * Bank Bus Machine PortSz Device
566 * ---- --- ------- ------ ------
567 * 0 60x GPCM 32 bit FLASH (SIMM - 4MB)
568 * 1 60x GPCM 32 bit unused
569 * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
570 * 3 60x SDRAM 64 bit unused
571 * 4 Local GPCM 8 bit IO (on board - 64k)
572 * 5 60x GPCM 8 bit unused
573 * 6 60x GPCM 8 bit unused
574 * 7 60x GPCM 8 bit unused
578 /*-----------------------------------------------------------------------
579 * BR0 - Base Register
580 * Ref: Section 10.3.1 on page 10-14
581 * OR0 - Option Register
582 * Ref: Section 10.3.2 on page 10-18
583 *-----------------------------------------------------------------------
586 /* Bank 0,1 - FLASH SIMM
588 * This expects the FLASH SIMM to be connected to *CS0
589 * It consists of 4 AM29F016D parts.
591 * Note: For the 8 MB SIMM, *CS1 is unused.
594 /* BR0 is configured as follows:
596 * - Base address of 0x40000000
598 * - Data errors checking is disabled
599 * - Read and write access
601 * - Access are handled by the memory controller according to MSEL
602 * - Not used for atomic operations
603 * - No data pipelining is done
606 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
611 /* OR0 is configured as follows:
614 * - *BCTL0 is asserted upon access to the current memory bank
615 * - *CW / *WE are negated a quarter of a clock earlier
616 * - *CS is output at the same time as the address lines
617 * - Uses a clock cycle length of 5
618 * - *PSDVAL is generated internally by the memory controller
619 * unless *GTA is asserted earlier externally.
620 * - Relaxed timing is generated by the GPCM for accesses
621 * initiated to this memory region.
622 * - One idle clock is inserted between a read access from the
623 * current bank and the next access.
625 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
632 /*-----------------------------------------------------------------------
633 * BR2 - Base Register
634 * Ref: Section 10.3.1 on page 10-14
635 * OR2 - Option Register
636 * Ref: Section 10.3.2 on page 10-16
637 *-----------------------------------------------------------------------
640 /* Bank 2 - SDRAM DIMM
643 * 64MB DIMM: P/N 1W-8864X8-4-P1-EST or
644 * MT4LSDT864AG-10EB1 (Micron)
646 * Note: *CS3 is unused for this DIMM
649 /* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
651 * - Base address of 0x00000000
652 * - 64 bit port size (60x bus only)
653 * - Data errors checking is disabled
654 * - Read and write access
656 * - Access are handled by the memory controller according to MSEL
657 * - Not used for atomic operations
658 * - No data pipelining is done
661 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
666 /* With a 16 MB DIMM, the OR2 is configured as follows:
669 * - 2 internal banks per device
670 * - Row start address bit is A9 with PSDMR[PBI] = 0
671 * - 11 row address lines
672 * - Back-to-back page mode
673 * - Internal bank interleaving within save device enabled
675 #if (CONFIG_SYS_SDRAM0_SIZE == 16)
676 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
678 ORxS_ROWST_PBI0_A9 |\
681 /* With a 16 MB DIMM, the PSDMR is configured as follows:
683 * - Page Based Interleaving,
685 * - Address Multiplexing where A5 is output on A14 pin
686 * (A6 on A15, and so on),
687 * - use address pins A16-A18 as bank select,
688 * - A9 is output on SDA10 during an ACTIVATE command,
689 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
690 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
692 * - earliest timing for READ/WRITE command after ACTIVATE command is
694 * - earliest timing for PRECHARGE after last data was read is 1 clock,
695 * - earliest timing for PRECHARGE after last data was written is 1 clock,
696 * - CAS Latency is 2.
699 /*-----------------------------------------------------------------------
700 * PSDMR - 60x Bus SDRAM Mode Register
701 * Ref: Section 10.3.3 on page 10-21
702 *-----------------------------------------------------------------------
704 #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
705 PSDMR_SDAM_A14_IS_A5 |\
706 PSDMR_BSMA_A16_A18 |\
707 PSDMR_SDA10_PBI0_A9 |\
714 #endif /* (CONFIG_SYS_SDRAM0_SIZE == 16) */
716 /* With a 64 MB DIMM, the OR2 is configured as follows:
719 * - 4 internal banks per device
720 * - Row start address bit is A8 with PSDMR[PBI] = 0
721 * - 12 row address lines
722 * - Back-to-back page mode
723 * - Internal bank interleaving within save device enabled
725 #if (CONFIG_SYS_SDRAM0_SIZE == 64)
726 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
728 ORxS_ROWST_PBI0_A8 |\
731 /* With a 64 MB DIMM, the PSDMR is configured as follows:
733 * - Page Based Interleaving,
735 * - Address Multiplexing where A5 is output on A14 pin
736 * (A6 on A15, and so on),
737 * - use address pins A14-A16 as bank select,
738 * - A9 is output on SDA10 during an ACTIVATE command,
739 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
740 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
742 * - earliest timing for READ/WRITE command after ACTIVATE command is
744 * - earliest timing for PRECHARGE after last data was read is 1 clock,
745 * - earliest timing for PRECHARGE after last data was written is 1 clock,
746 * - CAS Latency is 2.
749 /*-----------------------------------------------------------------------
750 * PSDMR - 60x Bus SDRAM Mode Register
751 * Ref: Section 10.3.3 on page 10-21
752 *-----------------------------------------------------------------------
754 #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
755 PSDMR_SDAM_A14_IS_A5 |\
756 PSDMR_BSMA_A14_A16 |\
757 PSDMR_SDA10_PBI0_A9 |\
764 #endif /* (CONFIG_SYS_SDRAM0_SIZE == 64) */
766 #define CONFIG_SYS_PSRT 0x0e
767 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
770 /*-----------------------------------------------------------------------
771 * BR4 - Base Register
772 * Ref: Section 10.3.1 on page 10-14
773 * OR4 - Option Register
774 * Ref: Section 10.3.2 on page 10-18
775 *-----------------------------------------------------------------------
777 /* Bank 4 - Onboard Memory Mapped IO controller
779 * This expects the onboard IO controller to connected to *CS4 and
781 * - Base address of 0xe0000000
782 * - 8 bit port size (local bus only)
783 * - Read and write access
785 * - Not used for atomic operations
786 * - No data pipelining is done
788 * - extended hold time
792 #ifdef CONFIG_SYS_IO_BASE
793 # define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
798 # define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
801 #endif /* CONFIG_SYS_IO_BASE */
802 #endif /* __CONFIG_H */