3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jmonkman@adventnetworks.com>
14 * Advent Networks, Inc. <http://www.adventnetworks.com>
15 * Oliver Brown <obrown@adventnetworks.com>
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 /*********************************************************************/
38 * This file contains the board configuartion for the GW8260 board.
43 * RESTRICTIONS/LIMITATIONS:
46 * Copyright (c) 2001, Advent Networks, Inc.
48 /*********************************************************************/
53 #define CONFIG_SYS_TEXT_BASE 0x40000000
55 /* Enable debug prints */
56 #undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
58 /* What is the oscillator's (UX2) frequency in Hz? */
59 #define CONFIG_8260_CLKIN (66 * 1000 * 1000)
61 /*-----------------------------------------------------------------------
62 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
63 *-----------------------------------------------------------------------
64 * What should MODCK_H be? It is dependent on the oscillator
65 * frequency, MODCK[1-3], and desired CPM and core frequencies.
66 * Here are some example values (all frequencies are in MHz):
68 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
69 * ------- ---------- --- --- ---- ----- ----- -----
70 * 0x5 0x5 66 133 133 Open Close Open
71 * 0x5 0x6 66 133 166 Open Open Close
72 * 0x5 0x7 66 133 200 Open Open Open
73 * 0x6 0x0 66 133 233 Close Close Close
74 * 0x6 0x1 66 133 266 Close Close Open
75 * 0x6 0x2 66 133 300 Close Open Close
77 #define CONFIG_SYS_SBC_MODCK_H 0x05
79 /* Define this if you want to boot from 0x00000100. If you don't define
80 * this, you will need to program the bootloader to 0xfff00000, and
81 * get the hardware reset config words at 0xfe000000. The simplest
82 * way to do that is to program the bootloader at both addresses.
83 * It is suggested that you just let U-Boot live at 0x00000000.
85 #define CONFIG_SYS_SBC_BOOT_LOW 1
87 /* What should the base address of the main FLASH be and how big is
88 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sbc8260/config.mk
89 * The main FLASH is whichever is connected to *CS0. U-Boot expects
90 * this to be the SIMM.
92 #define CONFIG_SYS_FLASH0_BASE 0x40000000
93 #define CONFIG_SYS_FLASH0_SIZE 8
95 /* Define CONFIG_SYS_FLASH_CHECKSUM to enable flash checksum during boot.
96 * Note: the 'flashchecksum' environment variable must also be set to 'y'.
98 #define CONFIG_SYS_FLASH_CHECKSUM
100 /* What should be the base address of SDRAM DIMM and how big is
103 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
104 #define CONFIG_SYS_SDRAM0_SIZE 64
108 * CONFIG_SYS_DRAM_TEST - enables the following tests.
110 * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
111 * Environment variable 'test_dram_data' must be
113 * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
114 * addressable. Environment variable
115 * 'test_dram_address' must be set to 'y'.
116 * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
117 * This test takes about 6 minutes to test 64 MB.
118 * Environment variable 'test_dram_walk' must be
121 #define CONFIG_SYS_DRAM_TEST
122 #if defined(CONFIG_SYS_DRAM_TEST)
123 #define CONFIG_SYS_DRAM_TEST_DATA
124 #define CONFIG_SYS_DRAM_TEST_ADDRESS
125 #define CONFIG_SYS_DRAM_TEST_WALK
126 #endif /* CONFIG_SYS_DRAM_TEST */
129 * GW8260 with 16 MB DIMM:
131 * 0x0000 0000 Exception Vector code, 8k
134 * 0x0000 2000 Free for Application Use
140 * 0x00F5 FF30 Monitor Stack (Growing downward)
141 * Monitor Stack Buffer (0x80)
142 * 0x00F5 FFB0 Board Info Data
143 * 0x00F6 0000 Malloc Arena
144 * : CONFIG_ENV_SECT_SIZE, 256k
145 * : CONFIG_SYS_MALLOC_LEN, 128k
146 * 0x00FC 0000 RAM Copy of Monitor Code
147 * : CONFIG_SYS_MONITOR_LEN, 256k
148 * 0x00FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
152 * GW8260 with 64 MB DIMM:
154 * 0x0000 0000 Exception Vector code, 8k
157 * 0x0000 2000 Free for Application Use
163 * 0x03F5 FF30 Monitor Stack (Growing downward)
164 * Monitor Stack Buffer (0x80)
165 * 0x03F5 FFB0 Board Info Data
166 * 0x03F6 0000 Malloc Arena
167 * : CONFIG_ENV_SECT_SIZE, 256k
168 * : CONFIG_SYS_MALLOC_LEN, 128k
169 * 0x03FC 0000 RAM Copy of Monitor Code
170 * : CONFIG_SYS_MONITOR_LEN, 256k
171 * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
176 * select serial console configuration
178 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
179 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
182 * if CONFIG_CONS_NONE is defined, then the serial console routines must
185 #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
186 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
187 #undef CONFIG_CONS_NONE /* define if console on neither */
188 #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
191 * select ethernet configuration
193 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
194 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
197 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
198 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
201 #undef CONFIG_ETHER_ON_SCC
202 #define CONFIG_ETHER_ON_FCC
203 #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
205 #ifdef CONFIG_ETHER_ON_SCC
206 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
207 #endif /* CONFIG_ETHER_ON_SCC */
209 #ifdef CONFIG_ETHER_ON_FCC
210 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
211 #define CONFIG_MII /* MII PHY management */
212 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
214 * Port pins used for bit-banged MII communictions (if applicable).
216 #define MDIO_PORT 2 /* Port C */
218 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
219 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
220 #define MDC_DECLARE MDIO_DECLARE
222 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
223 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
224 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
226 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
227 else iop->pdat &= ~0x00400000
229 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
230 else iop->pdat &= ~0x00200000
232 #define MIIDELAY udelay(1)
233 #endif /* CONFIG_ETHER_ON_FCC */
235 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
240 * - Select bus for bd/buffers (see 28-13)
241 * - Enable Full Duplex in FSMR
243 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
244 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
245 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
246 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
248 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
253 * - Select bus for bd/buffers (see 28-13)
254 * - Enable Full Duplex in FSMR
256 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
257 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
258 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
259 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
261 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
263 /* Define this to reserve an entire FLASH sector (256 KB) for
264 * environment variables. Otherwise, the environment will be
265 * put in the same sector as U-Boot, and changing variables
266 * will erase U-Boot temporarily
268 #define CONFIG_ENV_IN_OWN_SECT
270 /* Define to allow the user to overwrite serial and ethaddr */
271 #define CONFIG_ENV_OVERWRITE
273 /* What should the console's baud rate be? */
274 #define CONFIG_BAUDRATE 115200
276 /* Ethernet MAC address - This is set to all zeros to force an
277 * an error if we use BOOTP without setting
280 #define CONFIG_ETHADDR 00:00:00:00:00:00
282 /* Set to a positive value to delay for running BOOTCOMMAND */
283 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
285 /* Be selective on what keys can delay or stop the autoboot process
288 #define CONFIG_AUTOBOOT_KEYED
289 #define CONFIG_AUTOBOOT_PROMPT \
290 "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
291 #define CONFIG_AUTOBOOT_STOP_STR " "
292 #undef CONFIG_AUTOBOOT_DELAY_STR
293 #define DEBUG_BOOTKEYS 0
298 #define CONFIG_BOOTP_SUBNETMASK
299 #define CONFIG_BOOTP_GATEWAY
300 #define CONFIG_BOOTP_HOSTNAME
301 #define CONFIG_BOOTP_BOOTPATH
303 #define CONFIG_BOOTP_BOOTFILESIZE
304 #define CONFIG_BOOTP_DNS
306 /* undef this to save memory */
307 #define CONFIG_SYS_LONGHELP
309 /* Monitor Command Prompt */
310 #define CONFIG_SYS_PROMPT "=> "
314 * Command line configuration.
316 #include <config_cmd_default.h>
318 #define CONFIG_CMD_BEDBUG
319 #define CONFIG_CMD_ELF
320 #define CONFIG_CMD_ASKENV
321 #define CONFIG_CMD_REGINFO
322 #define CONFIG_CMD_IMMAP
323 #define CONFIG_CMD_MII
325 #undef CONFIG_CMD_KGDB
328 /* Where do the internal registers live? */
329 #define CONFIG_SYS_IMMR 0xf0000000
331 /* Use the HUSH parser */
332 #define CONFIG_SYS_HUSH_PARSER
333 #ifdef CONFIG_SYS_HUSH_PARSER
334 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
337 /* What is the address of IO controller */
338 #define CONFIG_SYS_IO_BASE 0xe0000000
340 /*****************************************************************************
342 * You should not have to modify any of the following settings
344 *****************************************************************************/
346 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
347 #define CONFIG_GW8260 1 /* on an GW8260 Board */
348 #define CONFIG_CPM2 1 /* Has a CPM2 */
351 * Miscellaneous configurable options
353 #if defined(CONFIG_CMD_KGDB)
354 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
356 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
359 /* Print Buffer Size */
360 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
362 #define CONFIG_SYS_MAXARGS 8 /* max number of command args */
364 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
366 /* Convert clocks to MHZ when passing board info to kernel.
367 * This must be defined for eariler 2.4 kernels (~2.4.4).
369 #define CONFIG_CLOCKS_IN_MHZ
371 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
372 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
375 /* memtest works from the end of the exception vector table
376 * to the end of the DRAM less monitor and malloc area
378 #define CONFIG_SYS_MEMTEST_START 0x2000
380 #define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
382 #define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
383 + CONFIG_SYS_MALLOC_LEN \
384 + CONFIG_ENV_SECT_SIZE \
385 + CONFIG_SYS_STACK_USAGE )
387 #define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
388 - CONFIG_SYS_MEM_END_USAGE )
390 /* valid baudrates */
391 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
394 * Low Level Configuration Settings
395 * (address mappings, register initial values, etc.)
396 * You should know what you are doing if you make changes here.
399 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
400 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
401 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
402 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE
404 /*-----------------------------------------------------------------------
405 * Hard Reset Configuration Words
407 #if defined(CONFIG_SYS_SBC_BOOT_LOW)
408 # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
410 # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
411 #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
413 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
414 #define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
415 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
416 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
418 #define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS11 | \
420 CONFIG_SYS_SBC_HRCW_IMMR | \
425 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \
426 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
429 #define CONFIG_SYS_HRCW_SLAVE1 0
430 #define CONFIG_SYS_HRCW_SLAVE2 0
431 #define CONFIG_SYS_HRCW_SLAVE3 0
432 #define CONFIG_SYS_HRCW_SLAVE4 0
433 #define CONFIG_SYS_HRCW_SLAVE5 0
434 #define CONFIG_SYS_HRCW_SLAVE6 0
435 #define CONFIG_SYS_HRCW_SLAVE7 0
437 /*-----------------------------------------------------------------------
438 * Definitions for initial stack pointer and data area (in DPRAM)
440 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
441 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
442 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
443 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
444 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
446 /*-----------------------------------------------------------------------
447 * Start addresses for the final memory configuration
448 * (Set up by the startup code)
449 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
450 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
452 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
454 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
455 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
458 * For booting Linux, the board info and command line data
459 * have to be in the first 8 MB of memory, since this is
460 * the maximum mapped by the Linux kernel during initialization.
462 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* Initial Memory map for Linux */
464 /*-----------------------------------------------------------------------
465 * FLASH and environment organization
467 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
468 #define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
470 #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
471 #define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
473 #define CONFIG_ENV_IS_IN_FLASH 1
475 #ifdef CONFIG_ENV_IN_OWN_SECT
476 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + (256 * 1024))
477 # define CONFIG_ENV_SECT_SIZE (256 * 1024)
479 # define CONFIG_ENV_SIZE (16 * 1024)/* Size of Environment Sector */
480 # define CONFIG_ENV_ADD ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SIZE)
481 # define CONFIG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size */
482 #endif /* CONFIG_ENV_IN_OWN_SECT */
484 /*-----------------------------------------------------------------------
485 * Cache Configuration
487 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
489 #if defined(CONFIG_CMD_KGDB)
490 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
493 /*-----------------------------------------------------------------------
494 * HIDx - Hardware Implementation-dependent Registers 2-11
495 *-----------------------------------------------------------------------
496 * HID0 also contains cache control - initially enable both caches and
497 * invalidate contents, then the final state leaves only the instruction
498 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
499 * but Soft reset does not.
501 * HID1 has only read-only information - nothing to set.
503 #define CONFIG_SYS_HID0_INIT (HID0_ICE |\
510 #define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
514 #define CONFIG_SYS_HID2 0
516 /*-----------------------------------------------------------------------
517 * RMR - Reset Mode Register
518 *-----------------------------------------------------------------------
520 #define CONFIG_SYS_RMR 0
522 /*-----------------------------------------------------------------------
523 * BCR - Bus Configuration 4-25
524 *-----------------------------------------------------------------------
526 #define CONFIG_SYS_BCR (BCR_ETM)
528 /*-----------------------------------------------------------------------
529 * SIUMCR - SIU Module Configuration 4-31
530 *-----------------------------------------------------------------------
532 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\
538 /*-----------------------------------------------------------------------
539 * SYPCR - System Protection Control 11-9
540 * SYPCR can only be written once after reset!
541 *-----------------------------------------------------------------------
542 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
544 #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
551 /*-----------------------------------------------------------------------
552 * TMCNTSC - Time Counter Status and Control 4-40
553 *-----------------------------------------------------------------------
554 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
555 * and enable Time Counter
557 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
562 /*-----------------------------------------------------------------------
563 * PISCR - Periodic Interrupt Status and Control 4-42
564 *-----------------------------------------------------------------------
565 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
568 #define CONFIG_SYS_PISCR (PISCR_PS |\
572 /*-----------------------------------------------------------------------
573 * SCCR - System Clock Control 9-8
574 *-----------------------------------------------------------------------
576 #define CONFIG_SYS_SCCR 0
578 /*-----------------------------------------------------------------------
579 * RCCR - RISC Controller Configuration 13-7
580 *-----------------------------------------------------------------------
582 #define CONFIG_SYS_RCCR 0
585 * Initialize Memory Controller:
587 * Bank Bus Machine PortSz Device
588 * ---- --- ------- ------ ------
589 * 0 60x GPCM 32 bit FLASH (SIMM - 4MB)
590 * 1 60x GPCM 32 bit unused
591 * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
592 * 3 60x SDRAM 64 bit unused
593 * 4 Local GPCM 8 bit IO (on board - 64k)
594 * 5 60x GPCM 8 bit unused
595 * 6 60x GPCM 8 bit unused
596 * 7 60x GPCM 8 bit unused
600 /*-----------------------------------------------------------------------
601 * BR0 - Base Register
602 * Ref: Section 10.3.1 on page 10-14
603 * OR0 - Option Register
604 * Ref: Section 10.3.2 on page 10-18
605 *-----------------------------------------------------------------------
608 /* Bank 0,1 - FLASH SIMM
610 * This expects the FLASH SIMM to be connected to *CS0
611 * It consists of 4 AM29F016D parts.
613 * Note: For the 8 MB SIMM, *CS1 is unused.
616 /* BR0 is configured as follows:
618 * - Base address of 0x40000000
620 * - Data errors checking is disabled
621 * - Read and write access
623 * - Access are handled by the memory controller according to MSEL
624 * - Not used for atomic operations
625 * - No data pipelining is done
628 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
633 /* OR0 is configured as follows:
636 * - *BCTL0 is asserted upon access to the current memory bank
637 * - *CW / *WE are negated a quarter of a clock earlier
638 * - *CS is output at the same time as the address lines
639 * - Uses a clock cycle length of 5
640 * - *PSDVAL is generated internally by the memory controller
641 * unless *GTA is asserted earlier externally.
642 * - Relaxed timing is generated by the GPCM for accesses
643 * initiated to this memory region.
644 * - One idle clock is inserted between a read access from the
645 * current bank and the next access.
647 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
654 /*-----------------------------------------------------------------------
655 * BR2 - Base Register
656 * Ref: Section 10.3.1 on page 10-14
657 * OR2 - Option Register
658 * Ref: Section 10.3.2 on page 10-16
659 *-----------------------------------------------------------------------
662 /* Bank 2 - SDRAM DIMM
665 * 64MB DIMM: P/N 1W-8864X8-4-P1-EST or
666 * MT4LSDT864AG-10EB1 (Micron)
668 * Note: *CS3 is unused for this DIMM
671 /* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
673 * - Base address of 0x00000000
674 * - 64 bit port size (60x bus only)
675 * - Data errors checking is disabled
676 * - Read and write access
678 * - Access are handled by the memory controller according to MSEL
679 * - Not used for atomic operations
680 * - No data pipelining is done
683 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
688 /* With a 16 MB DIMM, the OR2 is configured as follows:
691 * - 2 internal banks per device
692 * - Row start address bit is A9 with PSDMR[PBI] = 0
693 * - 11 row address lines
694 * - Back-to-back page mode
695 * - Internal bank interleaving within save device enabled
697 #if (CONFIG_SYS_SDRAM0_SIZE == 16)
698 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
700 ORxS_ROWST_PBI0_A9 |\
703 /* With a 16 MB DIMM, the PSDMR is configured as follows:
705 * - Page Based Interleaving,
707 * - Address Multiplexing where A5 is output on A14 pin
708 * (A6 on A15, and so on),
709 * - use address pins A16-A18 as bank select,
710 * - A9 is output on SDA10 during an ACTIVATE command,
711 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
712 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
714 * - earliest timing for READ/WRITE command after ACTIVATE command is
716 * - earliest timing for PRECHARGE after last data was read is 1 clock,
717 * - earliest timing for PRECHARGE after last data was written is 1 clock,
718 * - CAS Latency is 2.
721 /*-----------------------------------------------------------------------
722 * PSDMR - 60x Bus SDRAM Mode Register
723 * Ref: Section 10.3.3 on page 10-21
724 *-----------------------------------------------------------------------
726 #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
727 PSDMR_SDAM_A14_IS_A5 |\
728 PSDMR_BSMA_A16_A18 |\
729 PSDMR_SDA10_PBI0_A9 |\
736 #endif /* (CONFIG_SYS_SDRAM0_SIZE == 16) */
738 /* With a 64 MB DIMM, the OR2 is configured as follows:
741 * - 4 internal banks per device
742 * - Row start address bit is A8 with PSDMR[PBI] = 0
743 * - 12 row address lines
744 * - Back-to-back page mode
745 * - Internal bank interleaving within save device enabled
747 #if (CONFIG_SYS_SDRAM0_SIZE == 64)
748 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
750 ORxS_ROWST_PBI0_A8 |\
753 /* With a 64 MB DIMM, the PSDMR is configured as follows:
755 * - Page Based Interleaving,
757 * - Address Multiplexing where A5 is output on A14 pin
758 * (A6 on A15, and so on),
759 * - use address pins A14-A16 as bank select,
760 * - A9 is output on SDA10 during an ACTIVATE command,
761 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
762 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
764 * - earliest timing for READ/WRITE command after ACTIVATE command is
766 * - earliest timing for PRECHARGE after last data was read is 1 clock,
767 * - earliest timing for PRECHARGE after last data was written is 1 clock,
768 * - CAS Latency is 2.
771 /*-----------------------------------------------------------------------
772 * PSDMR - 60x Bus SDRAM Mode Register
773 * Ref: Section 10.3.3 on page 10-21
774 *-----------------------------------------------------------------------
776 #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
777 PSDMR_SDAM_A14_IS_A5 |\
778 PSDMR_BSMA_A14_A16 |\
779 PSDMR_SDA10_PBI0_A9 |\
786 #endif /* (CONFIG_SYS_SDRAM0_SIZE == 64) */
788 #define CONFIG_SYS_PSRT 0x0e
789 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
792 /*-----------------------------------------------------------------------
793 * BR4 - Base Register
794 * Ref: Section 10.3.1 on page 10-14
795 * OR4 - Option Register
796 * Ref: Section 10.3.2 on page 10-18
797 *-----------------------------------------------------------------------
799 /* Bank 4 - Onboard Memory Mapped IO controller
801 * This expects the onboard IO controller to connected to *CS4 and
803 * - Base address of 0xe0000000
804 * - 8 bit port size (local bus only)
805 * - Read and write access
807 * - Not used for atomic operations
808 * - No data pipelining is done
810 * - extended hold time
814 #ifdef CONFIG_SYS_IO_BASE
815 # define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
820 # define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
823 #endif /* CONFIG_SYS_IO_BASE */
826 * Internal Definitions
830 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
831 #define BOOTFLAG_WARM 0x02 /* Software reboot */
833 #endif /* __CONFIG_H */