2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <config_cmd_default.h>
12 #define CONFIG_LS102XA
14 #define CONFIG_SYS_GENERIC_BOARD
16 #define CONFIG_DISPLAY_CPUINFO
17 #define CONFIG_DISPLAY_BOARDINFO
19 #define CONFIG_SKIP_LOWLEVEL_INIT
20 #define CONFIG_BOARD_EARLY_INIT_F
23 * Size of malloc() pool
25 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
27 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
28 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
31 * Generic Timer Definitions
33 #define GENERIC_TIMER_CLK 12500000
35 #define CONFIG_SYS_CLK_FREQ 100000000
36 #define CONFIG_DDR_CLK_FREQ 100000000
38 #ifndef CONFIG_SYS_TEXT_BASE
39 #define CONFIG_SYS_TEXT_BASE 0x67f80000
42 #define CONFIG_NR_DRAM_BANKS 1
43 #define PHYS_SDRAM 0x80000000
44 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
46 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
49 #define CONFIG_SYS_HAS_SERDES
51 #define CONFIG_FSL_CAAM /* Enable CAAM */
53 #if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
60 #define CONFIG_FSL_IFC
61 #define CONFIG_SYS_FLASH_BASE 0x60000000
62 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
64 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
65 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
69 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
71 /* NOR Flash Timing Params */
72 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
74 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
75 FTIM0_NOR_TEADC(0x5) | \
76 FTIM0_NOR_TAVDS(0x0) | \
78 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
79 FTIM1_NOR_TRAD_NOR(0x1A) | \
80 FTIM1_NOR_TSEQRAD_NOR(0x13))
81 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
82 FTIM2_NOR_TCH(0x4) | \
83 FTIM2_NOR_TWP(0x1c) | \
85 #define CONFIG_SYS_NOR_FTIM3 0
87 #define CONFIG_FLASH_CFI_DRIVER
88 #define CONFIG_SYS_FLASH_CFI
89 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
90 #define CONFIG_SYS_FLASH_QUIET_TEST
91 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
93 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
94 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
95 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
96 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
98 #define CONFIG_SYS_FLASH_EMPTY_INFO
99 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
101 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
105 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
106 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
108 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
109 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
113 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
114 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
115 CSOR_NOR_NOR_MODE_AVD_NOR | \
118 /* CPLD Timing parameters for IFC GPCM */
119 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
120 FTIM0_GPCM_TEADC(0xf) | \
121 FTIM0_GPCM_TEAHC(0xf))
122 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
123 FTIM1_GPCM_TRAD(0x3f))
124 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
125 FTIM2_GPCM_TCH(0xf) | \
126 FTIM2_GPCM_TWP(0xff))
127 #define CONFIG_SYS_FPGA_FTIM3 0x0
128 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
129 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
130 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
131 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
132 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
133 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
134 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
135 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
136 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
137 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
138 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
139 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
140 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
141 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
142 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
143 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
148 #define CONFIG_CONS_INDEX 1
149 #define CONFIG_SYS_NS16550
150 #define CONFIG_SYS_NS16550_SERIAL
151 #define CONFIG_SYS_NS16550_REG_SIZE 1
152 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
154 #define CONFIG_BAUDRATE 115200
159 #define CONFIG_CMD_I2C
160 #define CONFIG_SYS_I2C
161 #define CONFIG_SYS_I2C_MXC
167 #define CONFIG_CMD_MMC
168 #define CONFIG_FSL_ESDHC
169 #define CONFIG_GENERIC_MMC
174 #define CONFIG_FSL_DCU_FB
176 #ifdef CONFIG_FSL_DCU_FB
178 #define CONFIG_CMD_BMP
179 #define CONFIG_CFB_CONSOLE
180 #define CONFIG_VGA_AS_SINGLE_DEVICE
181 #define CONFIG_VIDEO_LOGO
182 #define CONFIG_VIDEO_BMP_LOGO
184 #define CONFIG_FSL_DCU_SII9022A
185 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
186 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
192 #define CONFIG_TSEC_ENET
194 #ifdef CONFIG_TSEC_ENET
196 #define CONFIG_MII_DEFAULT_TSEC 1
197 #define CONFIG_TSEC1 1
198 #define CONFIG_TSEC1_NAME "eTSEC1"
199 #define CONFIG_TSEC2 1
200 #define CONFIG_TSEC2_NAME "eTSEC2"
201 #define CONFIG_TSEC3 1
202 #define CONFIG_TSEC3_NAME "eTSEC3"
204 #define TSEC1_PHY_ADDR 2
205 #define TSEC2_PHY_ADDR 0
206 #define TSEC3_PHY_ADDR 1
208 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
209 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
210 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
212 #define TSEC1_PHYIDX 0
213 #define TSEC2_PHYIDX 0
214 #define TSEC3_PHYIDX 0
216 #define CONFIG_ETHPRIME "eTSEC1"
218 #define CONFIG_PHY_GIGE
219 #define CONFIG_PHYLIB
220 #define CONFIG_PHY_ATHEROS
222 #define CONFIG_HAS_ETH0
223 #define CONFIG_HAS_ETH1
224 #define CONFIG_HAS_ETH2
227 #define CONFIG_CMD_PING
228 #define CONFIG_CMD_DHCP
229 #define CONFIG_CMD_MII
230 #define CONFIG_CMD_NET
232 #define CONFIG_CMDLINE_TAG
233 #define CONFIG_CMDLINE_EDITING
234 #define CONFIG_CMD_IMLS
236 #define CONFIG_HWCONFIG
237 #define HWCONFIG_BUFFER_SIZE 128
239 #define CONFIG_BOOTDELAY 3
241 #define CONFIG_EXTRA_ENV_SETTINGS \
242 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
243 "initrd_high=0xcfffffff\0" \
244 "fdt_high=0xcfffffff\0"
247 * Miscellaneous configurable options
249 #define CONFIG_SYS_LONGHELP /* undef to save memory */
250 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
251 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
252 #define CONFIG_SYS_PROMPT "=> "
253 #define CONFIG_AUTO_COMPLETE
254 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
255 #define CONFIG_SYS_PBSIZE \
256 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
257 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
258 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
260 #define CONFIG_CMD_ENV_EXISTS
261 #define CONFIG_CMD_GREPENV
262 #define CONFIG_CMD_MEMINFO
263 #define CONFIG_CMD_MEMTEST
264 #define CONFIG_SYS_MEMTEST_START 0x80000000
265 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
267 #define CONFIG_SYS_LOAD_ADDR 0x82000000
271 * The stack sizes are set up in start.S using the settings below
273 #define CONFIG_STACKSIZE (30 * 1024)
275 #define CONFIG_SYS_INIT_SP_OFFSET \
276 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
277 #define CONFIG_SYS_INIT_SP_ADDR \
278 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
280 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
282 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
287 #define CONFIG_ENV_OVERWRITE
289 #define CONFIG_ENV_IS_IN_FLASH
290 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
291 #define CONFIG_ENV_SIZE 0x20000
292 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
294 #define CONFIG_OF_LIBFDT
295 #define CONFIG_OF_BOARD_SETUP
296 #define CONFIG_CMD_BOOTZ
298 #define CONFIG_MISC_INIT_R
300 /* Hash command with SHA acceleration supported in hardware */
301 #define CONFIG_CMD_HASH
302 #define CONFIG_SHA_HW_ACCEL
304 #ifdef CONFIG_SECURE_BOOT
305 #define CONFIG_CMD_BLOB