3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 /* External logbuffer support */
32 #define CONFIG_LOGBUFFER
34 /* Reserve space for the logbuffer */
35 #ifdef CONFIG_LOGBUFFER
36 #define CONFIG_PRAM 20
40 * High Level Configuration Options
44 #define CONFIG_MPC823 1 /* This is a MPC823E CPU */
45 #define CONFIG_LWMON 1 /* ...on a LWMON board */
47 #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
49 #define CONFIG_LCD 1 /* use LCD controller ... */
50 #define CONFIG_HLD1045 1 /* ... with a HLD1045 display */
53 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
55 #define CONFIG_8xx_CONS_SCC2
58 #define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */
60 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
62 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
64 /* pre-boot commands */
65 #define CONFIG_PREBOOT "setenv bootdelay 15"
67 #undef CONFIG_BOOTARGS
70 #define CONFIG_POST (CFG_POST_CACHE | \
81 #define CONFIG_BOOTCOMMAND "run flash_self"
83 #define CONFIG_EXTRA_ENV_SETTINGS \
84 "kernel_addr=40040000\0" \
85 "ramdisk_addr=40100000\0" \
88 "key_cmd#=setenv addfb setenv bootargs \\$(bootargs) console=tty0\0" \
90 "key_cmd3=echo *** Entering Test Mode ***;" \
91 "setenv add_misc setenv bootargs \\$(bootargs) testmode\0" \
92 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
93 "ramargs=setenv bootargs root=/dev/ram rw\0" \
94 "addfb=setenv bootargs $(bootargs) console=ttyS1,$(baudrate)\0" \
95 "addip=setenv bootargs $(bootargs) " \
96 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off " \
98 "add_wdt=setenv bootargs $(bootargs) $(wdt_args)\0" \
99 "flash_nfs=run nfsargs addip add_wdt addfb;" \
100 "bootm $(kernel_addr)\0" \
101 "flash_self=run ramargs addip add_wdt addfb;" \
102 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
103 "net_nfs=tftp 100000 /tftpboot/pImage.lwmon;" \
104 "run nfsargs addip add_wdt addfb;bootm\0" \
105 "rootpath=/opt/eldk/ppc_8xx\0" \
106 "load=tftp 100000 /tftpboot/u-boot.bin\0" \
107 "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $(filesize)\0" \
108 "wdt_args=wdt_8xx=off\0" \
111 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
112 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
114 #define CONFIG_WATCHDOG 1 /* watchdog enabled */
116 #undef CONFIG_STATUS_LED /* Status LED disabled */
118 /* enable I2C and select the hardware/software driver */
119 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
120 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
122 #ifdef CONFIG_HARD_I2C
124 * Hardware (CPM) I2C driver configuration
126 # define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
127 # define CFG_I2C_SLAVE 0xFE
128 #endif /* CONFIG_HARD_I2C */
130 #ifdef CONFIG_SOFT_I2C
132 * Software (bit-bang) I2C driver configuration
134 #define PB_SCL 0x00000020 /* PB 26 */
135 #define PB_SDA 0x00000010 /* PB 27 */
137 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
138 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
139 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
140 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
141 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
142 else immr->im_cpm.cp_pbdat &= ~PB_SDA
143 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
144 else immr->im_cpm.cp_pbdat &= ~PB_SCL
145 #define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */
146 #endif /* CONFIG_SOFT_I2C */
149 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
152 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
154 #define CFG_CMD_POST_DIAG 0
157 #ifdef CONFIG_8xx_CONS_SCC2 /* Can't use ethernet, then */
158 #define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \
166 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
175 #define CONFIG_MAC_PARTITION
176 #define CONFIG_DOS_PARTITION
178 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
180 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
181 #include <cmd_confdefs.h>
183 /*----------------------------------------------------------------------*/
186 * Miscellaneous configurable options
188 #define CFG_LONGHELP /* undef to save memory */
189 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
191 #undef CFG_HUSH_PARSER /* enable "hush" shell */
192 #ifdef CFG_HUSH_PARSER
193 #define CFG_PROMPT_HUSH_PS2 "> "
196 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
197 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
199 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
201 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
202 #define CFG_MAXARGS 16 /* max number of command args */
203 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
205 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
206 #define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
208 #define CFG_LOAD_ADDR 0x00100000 /* default load address */
210 #define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
212 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
214 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
217 * Low Level Configuration Settings
218 * (address mappings, register initial values, etc.)
219 * You should know what you are doing if you make changes here.
221 /*-----------------------------------------------------------------------
222 * Internal Memory Mapped Register
224 #define CFG_IMMR 0xFFF00000
226 /*-----------------------------------------------------------------------
227 * Definitions for initial stack pointer and data area (in DPRAM)
229 #define CFG_INIT_RAM_ADDR CFG_IMMR
230 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
231 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
232 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
233 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
235 /*-----------------------------------------------------------------------
236 * Start addresses for the final memory configuration
237 * (Set up by the startup code)
238 * Please note that CFG_SDRAM_BASE _must_ start at 0
240 #define CFG_SDRAM_BASE 0x00000000
241 #define CFG_FLASH_BASE 0x40000000
242 #if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
243 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
245 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
247 #define CFG_MONITOR_BASE CFG_FLASH_BASE
248 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
251 * For booting Linux, the board info and command line data
252 * have to be in the first 8 MB of memory, since this is
253 * the maximum mapped by the Linux kernel during initialization.
255 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
256 /*-----------------------------------------------------------------------
259 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
260 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
262 #define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
263 #define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
266 /* Put environment in flash which is much faster to boot */
267 #define CFG_ENV_IS_IN_FLASH 1
268 #define CFG_ENV_ADDR 0x40040000 /* Address of Environment Sector */
269 #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */
270 #define CFG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */
272 /* Environment in EEPROM */
273 #define CFG_ENV_IS_IN_EEPROM 1
274 #define CFG_ENV_OFFSET 0
275 #define CFG_ENV_SIZE 2048
277 /*-----------------------------------------------------------------------
278 * I2C/EEPROM Configuration
281 #define CFG_I2C_AUDIO_ADDR 0x28 /* Audio volume control */
282 #define CFG_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */
283 #define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
284 #define CFG_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */
285 #define CFG_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */
286 #define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
287 #define CFG_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */
289 #define CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */
290 #ifdef CONFIG_USE_FRAM /* use FRAM */
291 #define CFG_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */
292 #define CFG_I2C_EEPROM_ADDR_LEN 2
293 #else /* use EEPROM */
294 #define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
295 #define CFG_I2C_EEPROM_ADDR_LEN 1
296 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
297 #endif /* CONFIG_USE_FRAM */
298 #define CFG_EEPROM_PAGE_WRITE_BITS 4
300 /*-----------------------------------------------------------------------
301 * Cache Configuration
303 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
304 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
305 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
308 /*-----------------------------------------------------------------------
309 * SYPCR - System Protection Control 11-9
310 * SYPCR can only be written once after reset!
311 *-----------------------------------------------------------------------
312 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
314 #if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */
315 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
316 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
318 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
321 /*-----------------------------------------------------------------------
322 * SIUMCR - SIU Module Configuration 11-6
323 *-----------------------------------------------------------------------
324 * PCMCIA config., multi-function pin tri-state
326 /* EARB, DBGC and DBPC are initialised by the HCW */
328 #define CFG_SIUMCR (SIUMCR_GB5E)
329 /*#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
331 /*-----------------------------------------------------------------------
332 * TBSCR - Time Base Status and Control 11-26
333 *-----------------------------------------------------------------------
334 * Clear Reference Interrupt Status, Timebase freezing enabled
336 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
338 /*-----------------------------------------------------------------------
339 * PISCR - Periodic Interrupt Status and Control 11-31
340 *-----------------------------------------------------------------------
341 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
343 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
345 /*-----------------------------------------------------------------------
346 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
347 *-----------------------------------------------------------------------
348 * Reset PLL lock status sticky bit, timer expired status bit and timer
349 * interrupt status bit, set PLL multiplication factor !
352 #define CFG_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */
354 ( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
355 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
356 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
357 PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
360 #define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*13200000)
362 /*-----------------------------------------------------------------------
363 * SCCR - System Clock and reset Control Register 15-27
364 *-----------------------------------------------------------------------
365 * Set clock output, timebase and RTC source and divider,
366 * power management and some other internal clocks
368 #define SCCR_MASK SCCR_EBDF11
370 #define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
371 SCCR_RTDIV | SCCR_RTSEL | \
372 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
373 SCCR_EBDF00 | SCCR_DFSYNC00 | \
374 SCCR_DFBRG00 | SCCR_DFNL000 | \
375 SCCR_DFNH000 | SCCR_DFLCD100 | \
378 /*-----------------------------------------------------------------------
379 * RTCSC - Real-Time Clock Status and Control Register 11-27
380 *-----------------------------------------------------------------------
382 /* 0x00C3 => 0x0003 */
383 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
386 /*-----------------------------------------------------------------------
387 * RCCR - RISC Controller Configuration Register 19-4
388 *-----------------------------------------------------------------------
390 #define CFG_RCCR 0x0000
392 /*-----------------------------------------------------------------------
393 * RMDS - RISC Microcode Development Support Control Register
394 *-----------------------------------------------------------------------
398 /*-----------------------------------------------------------------------
401 *-----------------------------------------------------------------------
403 #define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
405 /*-----------------------------------------------------------------------
407 *-----------------------------------------------------------------------
410 #define CFG_PCMCIA_MEM_ADDR (0x50000000)
411 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
412 #define CFG_PCMCIA_DMA_ADDR (0x54000000)
413 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
414 #define CFG_PCMCIA_ATTRB_ADDR (0x58000000)
415 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
416 #define CFG_PCMCIA_IO_ADDR (0x5C000000)
417 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
419 /*-----------------------------------------------------------------------
420 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
421 *-----------------------------------------------------------------------
424 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
426 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
427 #undef CONFIG_IDE_LED /* LED for ide not supported */
428 #undef CONFIG_IDE_RESET /* reset for ide not supported */
430 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
431 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
433 #define CFG_ATA_IDE0_OFFSET 0x0000
435 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
437 /* Offset for data I/O */
438 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
440 /* Offset for normal register accesses */
441 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
443 /* Offset for alternate registers */
444 #define CFG_ATA_ALT_OFFSET 0x0100
446 /*-----------------------------------------------------------------------
448 *-----------------------------------------------------------------------
451 /*#define CFG_DER 0x2002000F*/
455 * Init Memory Controller:
457 * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
460 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
461 #define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */
463 /* used to re-map FLASH:
464 * restrict access enough to keep SRAM working (if any)
465 * but not too much to meddle with FLASH accesses
467 #define CFG_REMAP_OR_AM 0xFF000000 /* OR addr mask */
468 #define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
470 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
471 #define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK)
473 #define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
475 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
477 /* 16 bit, bank valid */
478 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
480 #define CFG_OR1_REMAP CFG_OR0_REMAP
481 #define CFG_OR1_PRELIM CFG_OR0_PRELIM
482 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
487 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
489 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
490 #define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */
491 #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
493 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */
495 #define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
496 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
499 * BR5/OR5: Touch Panel
501 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
503 #define TOUCHPNL_BASE 0x20000000
504 #define TOUCHPNL_OR_AM 0xFFFF8000
505 #define TOUCHPNL_TIMING OR_SCY_0_CLK
507 #define CFG_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
509 #define CFG_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
511 #define CFG_MEMORY_75
516 * Memory Periodic Timer Prescaler
519 /* periodic timer for refresh */
520 #define CFG_MPTPR 0x200
523 * MAMR settings for SDRAM
526 #define CFG_MAMR_8COL 0x80802114
527 #define CFG_MAMR_9COL 0x80904114
530 * MAR setting for SDRAM
532 #define CFG_MAR 0x00000088
535 * Internal Definitions
539 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
540 #define BOOTFLAG_WARM 0x02 /* Software reboot */
542 #endif /* __CONFIG_H */