2 * Copyright (c) 2008 Nuovation System Designs, LLC
3 * Grant Erickson <gerickson@nuovations.com>
5 * (C) Copyright 2007-2008
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /************************************************************************
28 * makalu.h - configuration for AMCC Makalu (405EX)
29 ***********************************************************************/
34 /*-----------------------------------------------------------------------
35 * High Level Configuration Options
36 *----------------------------------------------------------------------*/
37 #define CONFIG_MAKALU 1 /* Board is Makalu */
38 #define CONFIG_4xx 1 /* ... PPC4xx family */
39 #define CONFIG_405EX 1 /* Specifc 405EX support*/
40 #define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */
43 * Include common defines/options for all AMCC eval boards
45 #define CONFIG_HOSTNAME makalu
46 #define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"
47 #include "amcc-common.h"
49 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
50 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
52 /*-----------------------------------------------------------------------
53 * Base addresses -- Note these are effective addresses where the
54 * actual resources get mapped (not physical addresses)
55 *----------------------------------------------------------------------*/
56 #define CONFIG_SYS_FLASH_BASE 0xFC000000
57 #define CONFIG_SYS_FPGA_BASE 0xF0000000
58 #define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
60 /*-----------------------------------------------------------------------
61 * Initial RAM & Stack Pointer Configuration Options
63 * There are traditionally three options for the primordial
64 * (i.e. initial) stack usage on the 405-series:
66 * 1) On-chip Memory (OCM) (i.e. SRAM)
70 * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
71 * the latter of which is less than desireable since it requires
72 * setting up the SDRAM and ECC in assembly code.
74 * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
75 * select on the External Bus Controller (EBC) and then select a
76 * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
77 * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
78 * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
79 * physical SDRAM to use (3).
80 *-----------------------------------------------------------------------*/
82 #define CONFIG_SYS_INIT_DCACHE_CS 4
84 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
85 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
87 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
88 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
90 #define CONFIG_SYS_INIT_RAM_END (4 << 10) /* 4 KiB */
91 #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
92 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
95 * If the data cache is being used for the primordial stack and global
96 * data area, the POST word must be placed somewhere else. The General
97 * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
98 * its compare and mask register contents across reset, so it is used
102 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
103 # define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
104 # define CONFIG_SYS_POST_ALT_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
106 # define CONFIG_SYS_INIT_EXTRA_SIZE 16
107 # define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
108 # define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 4)
109 # define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
110 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
112 /*-----------------------------------------------------------------------
114 *----------------------------------------------------------------------*/
115 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no ext. clk */
116 /* define this if you want console on UART1 */
117 #undef CONFIG_UART1_CONSOLE
119 /*-----------------------------------------------------------------------
121 *----------------------------------------------------------------------*/
122 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
124 /*-----------------------------------------------------------------------
126 *----------------------------------------------------------------------*/
127 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
128 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
130 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
131 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
132 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
134 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
135 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
137 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
138 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
140 #ifdef CONFIG_ENV_IS_IN_FLASH
141 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
142 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
143 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
145 /* Address and size of Redundant Environment Sector */
146 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
147 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
148 #endif /* CONFIG_ENV_IS_IN_FLASH */
150 /*-----------------------------------------------------------------------
152 *----------------------------------------------------------------------*/
153 #define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
155 #define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
156 #define CONFIG_SYS_SDRAM0_MB1CF_BASE ((128 << 20) + CONFIG_SYS_SDRAM_BASE)
158 /* DDR1/2 SDRAM Device Control Register Data Values */
159 #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
160 SDRAM_RXBAS_SDSZ_128MB | \
161 SDRAM_RXBAS_SDAM_MODE2 | \
162 SDRAM_RXBAS_SDBE_ENABLE)
163 #define CONFIG_SYS_SDRAM0_MB1CF ((CONFIG_SYS_SDRAM0_MB1CF_BASE >> 3) | \
164 SDRAM_RXBAS_SDSZ_128MB | \
165 SDRAM_RXBAS_SDAM_MODE2 | \
166 SDRAM_RXBAS_SDBE_ENABLE)
167 #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
168 #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
169 #define CONFIG_SYS_SDRAM0_MCOPT1 0x04322000
170 #define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
171 #define CONFIG_SYS_SDRAM0_MODT0 0x01800000
172 #define CONFIG_SYS_SDRAM0_MODT1 0x00000000
173 #define CONFIG_SYS_SDRAM0_CODT 0x0080f837
174 #define CONFIG_SYS_SDRAM0_RTR 0x06180000
175 #define CONFIG_SYS_SDRAM0_INITPLR0 0xa8380000
176 #define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400
177 #define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000
178 #define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000
179 #define CONFIG_SYS_SDRAM0_INITPLR4 0x81010404
180 #define CONFIG_SYS_SDRAM0_INITPLR5 0x81000542
181 #define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400
182 #define CONFIG_SYS_SDRAM0_INITPLR7 0x8D080000
183 #define CONFIG_SYS_SDRAM0_INITPLR8 0x8D080000
184 #define CONFIG_SYS_SDRAM0_INITPLR9 0x8D080000
185 #define CONFIG_SYS_SDRAM0_INITPLR10 0x8D080000
186 #define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442
187 #define CONFIG_SYS_SDRAM0_INITPLR12 0x81010780
188 #define CONFIG_SYS_SDRAM0_INITPLR13 0x81010400
189 #define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
190 #define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
191 #define CONFIG_SYS_SDRAM0_RQDC 0x80000038
192 #define CONFIG_SYS_SDRAM0_RFDC 0x00000209
193 #define CONFIG_SYS_SDRAM0_RDCC 0x40000000
194 #define CONFIG_SYS_SDRAM0_DLCR 0x030000a5
195 #define CONFIG_SYS_SDRAM0_CLKTR 0x80000000
196 #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
197 #define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
198 #define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
199 #define CONFIG_SYS_SDRAM0_SDTR3 0x080b0d1a
200 #define CONFIG_SYS_SDRAM0_MMODE 0x00000442
201 #define CONFIG_SYS_SDRAM0_MEMODE 0x00000404
203 /*-----------------------------------------------------------------------
205 *----------------------------------------------------------------------*/
206 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
208 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
209 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
210 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
212 /* Standard DTT sensor configuration */
213 #define CONFIG_DTT_DS1775 1
214 #define CONFIG_DTT_SENSORS { 0 }
215 #define CONFIG_SYS_I2C_DTT_ADDR 0x48
217 /* RTC configuration */
218 #define CONFIG_RTC_X1205 1
219 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f
221 /*-----------------------------------------------------------------------
223 *----------------------------------------------------------------------*/
224 #define CONFIG_M88E1111_PHY 1
225 #define CONFIG_IBM_EMAC4_V4 1
226 #define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
227 #define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */
229 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
230 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
232 #define CONFIG_HAS_ETH0 1
234 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
235 #define CONFIG_PHY1_ADDR 0
238 * Default environment variables
240 #define CONFIG_EXTRA_ENV_SETTINGS \
241 CONFIG_AMCC_DEF_ENV \
242 CONFIG_AMCC_DEF_ENV_POWERPC \
243 CONFIG_AMCC_DEF_ENV_PPC_OLD \
244 CONFIG_AMCC_DEF_ENV_NOR_UPD \
245 "kernel_addr=fc000000\0" \
246 "fdt_addr=fc1e0000\0" \
247 "ramdisk_addr=fc200000\0" \
248 "pciconfighost=1\0" \
249 "pcie_mode=RP:RP\0" \
253 * Commands additional to the ones defined in amcc-common.h
255 #define CONFIG_CMD_DATE
256 #define CONFIG_CMD_DTT
257 #define CONFIG_CMD_LOG
258 #define CONFIG_CMD_PCI
259 #define CONFIG_CMD_SNTP
262 #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
263 CONFIG_SYS_POST_CPU | \
264 CONFIG_SYS_POST_ETHER | \
265 CONFIG_SYS_POST_I2C | \
266 CONFIG_SYS_POST_MEMORY | \
267 CONFIG_SYS_POST_UART)
269 /* Define here the base-addresses of the UARTs to test in POST */
270 #define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE}
272 #define CONFIG_LOGBUFFER
273 #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
275 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
277 /*-----------------------------------------------------------------------
279 *----------------------------------------------------------------------*/
280 #define CONFIG_PCI /* include pci support */
281 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
282 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
283 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
285 /*-----------------------------------------------------------------------
287 *----------------------------------------------------------------------*/
288 #define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
289 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
291 #define CONFIG_SYS_PCIE0_CFGBASE 0xa0000000 /* remote access */
292 #define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000 /* local access */
293 #define CONFIG_SYS_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
295 #define CONFIG_SYS_PCIE1_CFGBASE 0xc0000000 /* remote access */
296 #define CONFIG_SYS_PCIE1_XCFGBASE 0xd0000000 /* local access */
297 #define CONFIG_SYS_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
299 #define CONFIG_SYS_PCIE0_UTLBASE 0xef502000
300 #define CONFIG_SYS_PCIE1_UTLBASE 0xef503000
302 /* base address of inbound PCIe window */
303 #define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
305 /*-----------------------------------------------------------------------
306 * External Bus Controller (EBC) Setup
307 *----------------------------------------------------------------------*/
308 /* Memory Bank 0 (NOR-FLASH) initialization */
309 #define CONFIG_SYS_EBC_PB0AP 0x08033700
310 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
312 /* Memory Bank 2 (CPLD) initialization */
313 #define CONFIG_SYS_EBC_PB2AP 0x9400C800
314 #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */
316 #define CONFIG_SYS_EBC_CFG 0x7FC00000 /* EBC0_CFG */
318 /*-----------------------------------------------------------------------
320 *----------------------------------------------------------------------*/
321 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
324 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
325 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
326 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
327 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
328 {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
329 {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
330 {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
331 {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
332 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
333 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
334 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
335 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
336 {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
337 {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
338 {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
339 {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
340 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
341 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
342 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
343 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
344 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
345 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
346 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
347 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
348 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
349 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
350 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
351 {GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
352 {GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 */ \
353 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \
354 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \
355 {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \
359 #define CONFIG_SYS_GPIO_PCIE_RST 23
360 #define CONFIG_SYS_GPIO_PCIE_CLKREQ 27
361 #define CONFIG_SYS_GPIO_PCIE_WAKE 28
363 #endif /* __CONFIG_H */