3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC8247 1
33 #define CONFIG_MPC8272_FAMILY 1
34 #define CONFIG_MGCOGE 1
36 #define CONFIG_CPM2 1 /* Has a CPM2 */
38 /* Do boardspecific init */
39 #define CONFIG_BOARD_EARLY_INIT_R 1
42 * Select serial console configuration
44 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
48 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
49 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
50 #undef CONFIG_CONS_NONE /* It's not on external UART */
51 #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
54 * Select ethernet configuration
56 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
57 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
60 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
61 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
64 #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
65 #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
66 #undef CONFIG_ETHER_NONE /* No external Ethernet */
68 #define CONFIG_ETHER_INDEX 4
69 #define CFG_SCC_TOUT_LOOP 10000000
71 # define CFG_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
73 #ifndef CONFIG_8260_CLKIN
74 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
77 #define CONFIG_BAUDRATE 115200
80 * Command line configuration.
82 #include <config_cmd_default.h>
84 #define CONFIG_CMD_ECHO
85 #define CONFIG_CMD_IMMAP
86 #define CONFIG_CMD_MII
87 #define CONFIG_CMD_PING
90 * Default environment settings
92 #define CONFIG_EXTRA_ENV_SETTINGS \
94 "u-boot_addr=100000\0" \
95 "kernel_addr=200000\0" \
97 "rootpath=/opt/eldk-4.2/ppc_82xx\0" \
98 "u-boot=/tftpboot/mgcoge/u-boot.bin\0" \
99 "bootfile=/tftpboot/mgcoge/uImage\0" \
100 "fdt_file=/tftpboot/mgcoge/mgcoge.dtb\0" \
101 "load=tftp ${u-boot_addr} ${u-boot}\0" \
102 "update=prot off fe000000 fe03ffff; era fe000000 fe03ffff; " \
103 "cp.b ${u-boot_addr} fe000000 ${filesize};" \
104 "prot on fe000000 fe03ffff\0" \
105 "ramargs=setenv bootargs root=/dev/ram rw\0" \
106 "nfsargs=setenv bootargs root=/dev/nfs rw " \
107 "nfsroot=${serverip}:${rootpath}\0" \
108 "addcon=setenv bootargs ${bootargs} console=ttyCPM0,,${baudrate}\0" \
109 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
110 "addip=setenv bootargs ${bootargs} " \
111 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
112 "${netmask}:${hostname}:${netdev}:off panic=1 " \
113 "console=${console}\0" \
114 "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
115 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcon;"\
116 "bootm ${kernel_addr} - ${fdt_addr}\0" \
117 "net_self=tftp ${kernel_addr} ${bootfile}; " \
118 "tftp ${fdt_addr} ${fdt_file}; " \
119 "tftp ${ramdisk_addr} ${ramdisk_file}; " \
120 "run ramargs addip; " \
121 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
123 #define CONFIG_BOOTCOMMAND "run net_nfs"
124 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
126 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
129 * Miscellaneous configurable options
131 #define CFG_HUSH_PARSER
132 #define CFG_PROMPT_HUSH_PS2 "> "
133 #define CFG_LONGHELP /* undef to save memory */
134 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
135 #if defined(CONFIG_CMD_KGDB)
136 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
138 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
140 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
141 #define CFG_MAXARGS 16 /* max number of command args */
142 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
144 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
145 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
147 #define CFG_LOAD_ADDR 0x100000 /* default load address */
149 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
151 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
153 #define CFG_SDRAM_BASE 0x00000000
154 #define CFG_FLASH_BASE 0xFE000000
155 #define CFG_FLASH_SIZE 32
156 #define CFG_FLASH_CFI
157 #define CFG_FLASH_CFI_DRIVER
158 #define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
159 #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
161 #define CFG_FLASH_BASE_1 0x50000000
162 #define CFG_FLASH_SIZE_1 64
164 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE_1 }
166 #define CFG_MONITOR_BASE TEXT_BASE
167 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
171 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
173 #define CFG_ENV_IS_IN_FLASH
175 #ifdef CFG_ENV_IS_IN_FLASH
176 #define CFG_ENV_SECT_SIZE 0x20000
177 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
178 #endif /* CFG_ENV_IS_IN_FLASH */
180 #define CFG_IMMR 0xF0000000
182 #define CFG_INIT_RAM_ADDR CFG_IMMR
183 #define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
184 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
185 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
186 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
188 /* Hard reset configuration word */
189 #define CFG_HRCW_MASTER 0x0604b211
192 #define CFG_HRCW_SLAVE1 0
193 #define CFG_HRCW_SLAVE2 0
194 #define CFG_HRCW_SLAVE3 0
195 #define CFG_HRCW_SLAVE4 0
196 #define CFG_HRCW_SLAVE5 0
197 #define CFG_HRCW_SLAVE6 0
198 #define CFG_HRCW_SLAVE7 0
200 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
201 #define BOOTFLAG_WARM 0x02 /* Software reboot */
203 #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
204 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
206 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
207 #if defined(CONFIG_CMD_KGDB)
208 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
211 #define CFG_HID0_INIT 0
212 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
216 #define CFG_SIUMCR 0x4020c200
217 #define CFG_SYPCR 0xFFFFFFC3
218 #define CFG_BCR 0x10000000
219 #define CFG_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
221 /*-----------------------------------------------------------------------
222 * RMR - Reset Mode Register 5-5
223 *-----------------------------------------------------------------------
224 * turn on Checkstop Reset Enable
228 /*-----------------------------------------------------------------------
229 * TMCNTSC - Time Counter Status and Control 4-40
230 *-----------------------------------------------------------------------
231 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
232 * and enable Time Counter
234 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
236 /*-----------------------------------------------------------------------
237 * PISCR - Periodic Interrupt Status and Control 4-42
238 *-----------------------------------------------------------------------
239 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
242 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
244 /*-----------------------------------------------------------------------
245 * RCCR - RISC Controller Configuration 13-7
246 *-----------------------------------------------------------------------
251 * Init Memory Controller:
253 * Bank Bus Machine PortSz Device
254 * ---- --- ------- ------ ------
255 * 0 60x GPCM 8 bit FLASH
256 * 1 60x SDRAM 32 bit SDRAM
257 * 3 60x GPCM 8 bit GPIO/PIGGY
258 * 5 60x GPCM 16 bit CFG-Flash
263 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
268 #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
275 /* Bank 1 - 60x bus SDRAM
277 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
278 #define CFG_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
280 #define CFG_MPTPR 0x1800
282 /*-----------------------------------------------------------------------------
283 * Address for Mode Register Set (MRS) command
284 *-----------------------------------------------------------------------------
286 #define CFG_MRS_OFFS 0x00000110
287 #define CFG_PSRT 0x0e
289 #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
294 #define CFG_OR1_PRELIM CFG_OR1
296 /* SDRAM initialization values
299 #define CFG_OR1 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
301 ORxS_ROWST_PBI0_A7 |\
304 #define CFG_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
305 PSDMR_BSMA_A14_A16 |\
306 PSDMR_SDA10_PBI0_A9 |\
314 /* GPIO/PIGGY on CS3 initialization values
316 #define CFG_PIGGY_BASE 0x30000000
317 #define CFG_PIGGY_SIZE 128
319 #define CFG_BR3_PRELIM ((CFG_PIGGY_BASE & BRx_BA_MSK) |\
320 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
322 #define CFG_OR3_PRELIM (MEG_TO_AM(CFG_PIGGY_SIZE) |\
323 ORxG_CSNT | ORxG_ACS_DIV2 |\
324 ORxG_SCY_3_CLK | ORxG_TRLX )
326 /* CFG-Flash on CS5 initialization values
328 #define CFG_BR5_PRELIM ((CFG_FLASH_BASE_1 & BRx_BA_MSK) |\
329 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
331 #define CFG_OR5_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE_1) |\
332 ORxG_CSNT | ORxG_ACS_DIV2 |\
333 ORxG_SCY_5_CLK | ORxG_TRLX )
335 #define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
337 /* pass open firmware flat tree */
338 #define CONFIG_OF_LIBFDT 1
339 #define CONFIG_OF_BOARD_SETUP 1
341 #define OF_CPU "PowerPC,8247@0"
342 #define OF_SOC "soc@f0000000"
343 #define OF_TBCLK (bd->bi_busfreq / 4)
344 #define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
346 #endif /* __CONFIG_H */