2 * (C) Copyright 2007-2009 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MPC5121ADS board configuration file
30 #define CONFIG_MPC5121ADS 1
32 * Memory map for the MPC5121ADS board:
34 * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
35 * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
36 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
37 * 0x8200_0000 - 0x8200_001F CPLD (32 B)
38 * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
39 * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
40 * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
41 * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
45 * High Level Configuration Options
47 #define CONFIG_E300 1 /* E300 Family */
48 #define CONFIG_MPC512X 1 /* MPC512X family */
49 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
50 #undef CONFIG_FSL_DIU_LOGO_BMP /* Don't include FSL DIU binary bmp */
55 #if defined(CONFIG_VIDEO)
56 #define CONFIG_CFB_CONSOLE
57 #define CONFIG_VGA_AS_SINGLE_DEVICE
60 /* CONFIG_PCI is defined at config time */
62 #ifdef CONFIG_MPC5121ADS_REV2
63 #define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */
65 #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
69 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
70 #define CONFIG_MISC_INIT_R
72 #define CONFIG_SYS_IMMR 0x80000000
73 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
75 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
76 #define CONFIG_SYS_MEMTEST_END 0x00400000
79 * DDR Setup - manually set all parameters as there's no SPD etc.
81 #ifdef CONFIG_MPC5121ADS_REV2
82 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
84 #define CONFIG_SYS_DDR_SIZE 512 /* MB */
86 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
87 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
89 /* DDR Controller Configuration
92 * [31:31] MDDRC Soft Reset: Diabled
93 * [30:30] DRAM CKE pin: Enabled
94 * [29:29] DRAM CLK: Enabled
95 * [28:28] Command Mode: Enabled (For initialization only)
96 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
97 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
98 * [20:19] Read Test: DON'T USE
99 * [18:18] Self Refresh: Enabled
100 * [17:17] 16bit Mode: Disabled
101 * [16:13] Ready Delay: 2
102 * [12:12] Half DQS Delay: Disabled
103 * [11:11] Quarter DQS Delay: Disabled
104 * [10:08] Write Delay: 2
105 * [07:07] Early ODT: Disabled
106 * [06:06] On DIE Termination: Disabled
107 * [05:05] FIFO Overflow Clear: DON'T USE here
108 * [04:04] FIFO Underflow Clear: DON'T USE here
109 * [03:03] FIFO Overflow Pending: DON'T USE here
110 * [02:02] FIFO Underlfow Pending: DON'T USE here
111 * [01:01] FIFO Overlfow Enabled: Enabled
112 * [00:00] FIFO Underflow Enabled: Enabled
114 * [31:16] DRAM Refresh Time: 0 CSB clocks
115 * [15:8] DRAM Command Time: 0 CSB clocks
116 * [07:00] DRAM Precharge Time: 0 CSB clocks
120 * [20:17] DRAM tWRT1:
127 * [22:19] DRAM tRTW1:
133 #ifdef CONFIG_MPC5121ADS_REV2
134 #define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00
135 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168
136 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864
138 #define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00
139 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
140 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
142 #define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E
144 #define CONFIG_SYS_DDRCMD_NOP 0x01380000
145 #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
146 #define CONFIG_SYS_DDRCMD_EM2 0x01020000
147 #define CONFIG_SYS_DDRCMD_EM3 0x01030000
148 #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000
149 #define CONFIG_SYS_DDRCMD_RFSH 0x01080000
150 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
151 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780
153 /* DDR Priority Manager Configuration */
154 #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
155 #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
156 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
157 #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
158 #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
159 #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
160 #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
161 #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
162 #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
163 #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
164 #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
165 #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
166 #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
167 #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
168 #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
169 #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
170 #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
171 #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
172 #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
173 #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
174 #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
175 #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
176 #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
179 * NOR FLASH on the Local Bus
181 #undef CONFIG_BKUP_FLASH
182 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
183 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
184 #ifdef CONFIG_BKUP_FLASH
185 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
186 #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */
188 #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
189 #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */
191 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
192 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
193 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
194 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
196 #undef CONFIG_SYS_FLASH_CHECKSUM
200 * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
202 #define CONFIG_CMD_NAND /* enable NAND support */
203 #define CONFIG_JFFS2_NAND /* with JFFS2 on it */
204 #define CONFIG_NAND_MPC5121_NFC
205 #define CONFIG_SYS_NAND_BASE 0x40000000
207 #define CONFIG_SYS_MAX_NAND_DEVICE 2
208 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
209 #define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
211 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
214 * Configuration parameters for MPC5121 NAND driver
216 #define CONFIG_FSL_NFC_WIDTH 1
217 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
218 #define CONFIG_FSL_NFC_SPARE_SIZE 64
219 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
222 * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
225 #define CONFIG_SYS_CPLD_BASE 0x82000000
226 #define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */
228 #define CONFIG_SYS_SRAM_BASE 0x30000000
229 #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
231 #define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
232 #define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
233 #define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */
235 /* Use SRAM for initial stack */
236 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */
237 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE /* End of used area in RAM */
239 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
240 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
241 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
243 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */
244 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
245 #ifdef CONFIG_FSL_DIU_FB
246 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
248 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
254 #define CONFIG_CONS_INDEX 1
255 #undef CONFIG_SERIAL_SOFTWARE_FIFO
258 * Serial console configuration
260 #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
261 #if CONFIG_PSC_CONSOLE != 3
262 #error CONFIG_PSC_CONSOLE must be 3
264 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
265 #define CONFIG_SYS_BAUDRATE_TABLE \
266 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
268 #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
269 #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
270 #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
271 #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
273 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
274 /* Use the HUSH parser */
275 #define CONFIG_SYS_HUSH_PARSER
276 #ifdef CONFIG_SYS_HUSH_PARSER
277 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
288 #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
289 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
290 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
291 #define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
292 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
293 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
294 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
295 #define CONFIG_SYS_PCI_IO_PHYS 0x84000000
296 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
299 #define CONFIG_PCI_PNP /* do pci plug-and-play */
301 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
306 #define CONFIG_HARD_I2C /* I2C with hardware support */
307 #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
308 #define CONFIG_I2C_MULTI_BUS
309 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
310 #define CONFIG_SYS_I2C_SLAVE 0x7F
312 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
316 * IIM - IC Identification Module
321 * EEPROM configuration
323 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
324 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
325 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
326 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
329 * Ethernet configuration
331 #define CONFIG_MPC512x_FEC 1
332 #define CONFIG_NET_MULTI
333 #define CONFIG_PHY_ADDR 0x1
334 #define CONFIG_MII 1 /* MII PHY management */
335 #define CONFIG_FEC_AN_TIMEOUT 1
336 #define CONFIG_HAS_ETH0
339 * Configure on-board RTC
341 #define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */
342 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
347 #define CONFIG_ENV_IS_IN_FLASH 1
348 /* This has to be a multiple of the Flash sector size */
349 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
350 #define CONFIG_ENV_SIZE 0x2000
351 #ifdef CONFIG_BKUP_FLASH
352 #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */
354 #define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
357 /* Address and size of Redundant Environment Sector */
358 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
359 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
361 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
362 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
364 #include <config_cmd_default.h>
366 #define CONFIG_CMD_ASKENV
367 #define CONFIG_CMD_DATE
368 #define CONFIG_CMD_DHCP
369 #define CONFIG_CMD_EEPROM
370 #define CONFIG_CMD_EXT2
371 #define CONFIG_CMD_I2C
372 #define CONFIG_CMD_IDE
373 #define CONFIG_CMD_JFFS2
374 #define CONFIG_CMD_MII
375 #define CONFIG_CMD_NFS
376 #define CONFIG_CMD_PING
377 #define CONFIG_CMD_REGINFO
379 #undef CONFIG_CMD_FUSE
381 #if defined(CONFIG_PCI)
382 #define CONFIG_CMD_PCI
386 * Dynamic MTD partition support
388 #define CONFIG_CMD_MTDPARTS
389 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
390 #define CONFIG_FLASH_CFI_MTD
391 #define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand"
396 * FC000000 - FEABFFFF 42.75 MiB User Data
397 * FEAC0000 - FFABFFFF 16 MiB Root File System
398 * FFAC0000 - FFEBFFFF 4 MiB Linux Kernel
399 * FFEC0000 - FFEFFFFF 256 KiB Device Tree
400 * FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env
402 * NAND flash layout: one big partition
404 #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \
409 "mpc5121.nand:-(data)"
412 #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
413 #define CONFIG_DOS_PARTITION
414 #define CONFIG_MAC_PARTITION
415 #define CONFIG_ISO_PARTITION
416 #endif /* defined(CONFIG_CMD_IDE) */
419 * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
420 * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
421 * to 0xFFFF, watchdog timeouts after about 64s. For details refer
422 * to chapter 36 of the MPC5121e Reference Manual.
424 /* #define CONFIG_WATCHDOG */ /* enable watchdog */
425 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
428 * Miscellaneous configurable options
430 #define CONFIG_SYS_LONGHELP /* undef to save memory */
431 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
432 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
434 #ifdef CONFIG_CMD_KGDB
435 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
437 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
441 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
442 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
443 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
444 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
447 * For booting Linux, the board info and command line data
448 * have to be in the first 8 MB of memory, since this is
449 * the maximum mapped by the Linux kernel during initialization.
451 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
453 /* Cache Configuration */
454 #define CONFIG_SYS_DCACHE_SIZE 32768
455 #define CONFIG_SYS_CACHELINE_SIZE 32
456 #ifdef CONFIG_CMD_KGDB
457 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
460 #define CONFIG_SYS_HID0_INIT 0x000000000
461 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
462 #define CONFIG_SYS_HID2 HID2_HBE
464 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
467 * Internal Definitions
471 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
472 #define BOOTFLAG_WARM 0x02 /* Software reboot */
474 #ifdef CONFIG_CMD_KGDB
475 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
476 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
480 * Environment Configuration
482 #define CONFIG_TIMESTAMP
484 #define CONFIG_HOSTNAME mpc5121ads
485 #define CONFIG_BOOTFILE mpc5121ads/uImage
486 #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
488 #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
490 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
491 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
493 #define CONFIG_BAUDRATE 115200
495 #define CONFIG_PREBOOT "echo;" \
496 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
499 #define CONFIG_EXTRA_ENV_SETTINGS \
500 "u-boot_addr_r=200000\0" \
501 "kernel_addr_r=600000\0" \
502 "fdt_addr_r=880000\0" \
503 "ramdisk_addr_r=900000\0" \
504 "u-boot_addr=FFF00000\0" \
505 "kernel_addr=FFAC0000\0" \
506 "fdt_addr=FFEC0000\0" \
507 "ramdisk_addr=FEAC0000\0" \
508 "ramdiskfile=mpc5121ads/uRamdisk\0" \
509 "u-boot=mpc5121ads/u-boot.bin\0" \
510 "bootfile=mpc5121ads/uImage\0" \
511 "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \
512 "rootpath=/opt/eldk/ppc_6xx\n" \
514 "consdev=ttyPSC0\0" \
515 "nfsargs=setenv bootargs root=/dev/nfs rw " \
516 "nfsroot=${serverip}:${rootpath}\0" \
517 "ramargs=setenv bootargs root=/dev/ram rw\0" \
518 "addip=setenv bootargs ${bootargs} " \
519 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
520 ":${hostname}:${netdev}:off panic=1\0" \
521 "addtty=setenv bootargs ${bootargs} " \
522 "console=${consdev},${baudrate}\0" \
523 "flash_nfs=run nfsargs addip addtty;" \
524 "bootm ${kernel_addr} - ${fdt_addr}\0" \
525 "flash_self=run ramargs addip addtty;" \
526 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
527 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
528 "tftp ${fdt_addr_r} ${fdtfile};" \
529 "run nfsargs addip addtty;" \
530 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
531 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
532 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
533 "tftp ${fdt_addr_r} ${fdtfile};" \
534 "run ramargs addip addtty;" \
535 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
536 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
537 "update=protect off ${u-boot_addr} +${filesize};" \
538 "era ${u-boot_addr} +${filesize};" \
539 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
540 "upd=run load update\0" \
543 #define CONFIG_BOOTCOMMAND "run flash_self"
545 #define CONFIG_OF_LIBFDT 1
546 #define CONFIG_OF_BOARD_SETUP 1
547 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
549 #define OF_CPU "PowerPC,5121@0"
550 #define OF_SOC_COMPAT "fsl,mpc5121-immr"
551 #define OF_TBCLK (bd->bi_busfreq / 4)
552 #define OF_STDOUT_PATH "/soc@80000000/serial@11300"
554 /*-----------------------------------------------------------------------
556 *-----------------------------------------------------------------------
559 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
560 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
561 #undef CONFIG_IDE_LED /* LED for IDE not supported */
563 #define CONFIG_IDE_RESET /* reset for IDE supported */
564 #define CONFIG_IDE_PREINIT
566 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
567 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
569 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
570 #define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
572 /* Offset for data I/O RefMan MPC5121EE Table 28-10 */
573 #define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
575 /* Offset for normal register accesses */
576 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
578 /* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
579 #define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
581 /* Interval between registers */
582 #define CONFIG_SYS_ATA_STRIDE 4
584 #define ATA_BASE_ADDR get_pata_base()
587 * Control register bit definitions
589 #define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
590 #define FSL_ATA_CTRL_ATA_RST_B 0x40000000
591 #define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
592 #define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
593 #define FSL_ATA_CTRL_DMA_PENDING 0x08000000
594 #define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
595 #define FSL_ATA_CTRL_DMA_WRITE 0x02000000
596 #define FSL_ATA_CTRL_IORDY_EN 0x01000000
598 #endif /* __CONFIG_H */