2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
6 * Configuration settings for the MX51-3Stack Freescale board.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/mx51.h>
29 /* High Level Configuration Options */
30 #define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */
31 #define CONFIG_SYS_APCS_GNU
34 #define CONFIG_MX51_BBG 1 /* in a mx51 */
35 #define CONFIG_FLASH_HEADER 1
36 #define CONFIG_FLASH_HEADER_OFFSET 0x400
37 #define CONFIG_FLASH_HEADER_BARKER 0xB1
39 #define CONFIG_ARCH_CPU_INIT
40 #define CONFIG_ARCH_MMU
42 #define CONFIG_SKIP_RELOCATE_UBOOT
44 #define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
46 #define CONFIG_DISPLAY_CPUINFO
47 #define CONFIG_DISPLAY_BOARDINFO
49 #define CONFIG_SYS_64BIT_VSPRINTF
51 #define BOARD_LATE_INIT
53 * Disabled for now due to build problems under Debian and a significant
54 * increase in the final file size: 144260 vs. 109536 Bytes.
57 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
58 #define CONFIG_REVISION_TAG 1
59 #define CONFIG_SETUP_MEMORY_TAGS 1
60 #define CONFIG_INITRD_TAG 1
63 * Size of malloc() pool
65 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
66 /* size in bytes reserved for initial data */
67 #define CONFIG_SYS_GBL_DATA_SIZE 128
72 #define CONFIG_MX51_UART 1
73 #define CONFIG_MX51_UART1 1
76 #define CONFIG_CMD_PING
77 #define CONFIG_CMD_DHCP
78 #define CONFIG_BOOTP_SUBNETMASK
79 #define CONFIG_BOOTP_GATEWAY
80 #define CONFIG_BOOTP_DNS
81 #define CONFIG_CMD_MII
82 #define CONFIG_CMD_NET
83 #define CONFIG_NET_RETRY_COUNT 100
84 #define CONFIG_CMD_I2C
87 * Android support Configs
89 #include <asm/arch/keypad.h>
91 #define CONFIG_FSL_ANDROID
93 #define CONFIG_MTD_DEVICE
94 #define CONFIG_MTD_PARTITIONS
97 #define CONFIG_MXC_KPD
98 #define CONFIG_MXC_KEYMAPPING \
100 KEY_1, KEY_2, KEY_3, KEY_F1, KEY_UP, KEY_F2, \
101 KEY_4, KEY_5, KEY_6, KEY_LEFT, KEY_SELECT, KEY_RIGHT, \
102 KEY_7, KEY_8, KEY_9, KEY_F3, KEY_DOWN, KEY_F4, \
103 KEY_0, KEY_OK, KEY_ESC, KEY_ENTER, KEY_MENU, KEY_BACK, \
107 KEY_3, KEY_2, KEY_0, KEY_OK, KEY_ESC, KEY_ENTER,
108 KEY_F1, KEY_4, KEY_6, KEY_5,
109 KEY_LEFT, KEY_1, KEY_ , KEY_8, KEY_9, KEY_RIGHT,
112 #define CONFIG_MXC_KPD_COLMAX 6
113 #define CONFIG_MXC_KPD_ROWMAX 4
114 #define CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC \
115 "setenv bootargs ${bootargs} root=/dev/mmcblk0p4 ip=off init=/init rootfstype=ext3 wvga"
116 #define CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC \
117 "run bootargs_base bootargs_android;mmc read 0 ${loadaddr} 0x800 0x1280;bootm"
118 #define CONFIG_ANDROID_RECOVERY_CMD_FILE "/recovery/command"
119 #define CONFIG_ANDROID_BOOTMOD_DELAY 3
120 #define CONFIG_ANDROID_CACHE_PARTITION_MMC 6
122 /* allow to overwrite serial and ethaddr */
123 #define CONFIG_ENV_OVERWRITE
124 #define CONFIG_CONS_INDEX 1
125 #define CONFIG_BAUDRATE 115200
126 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
128 /***********************************************************
130 ***********************************************************/
132 #include <config_cmd_default.h>
134 #define CONFIG_CMD_PING
135 #define CONFIG_CMD_DHCP
136 /* Enable below configure when supporting nand */
137 /* #define CONFIG_CMD_NAND */
138 #define CONFIG_CMD_MMC
139 #define CONFIG_CMD_ENV
141 #undef CONFIG_CMD_IMLS
143 #define CONFIG_BOOTDELAY 3
145 #define CONFIG_PRIME "FEC0"
147 #define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
148 #define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
150 #define CONFIG_EXTRA_ENV_SETTINGS \
153 "uboot_addr=0xa0000000\0" \
154 "uboot=u-boot.bin\0" \
156 "rd_loadaddr=0x90B00000\0" \
157 "nfsroot=/opt/eldk/arm\0" \
158 "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
159 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
160 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
161 "bootargs_android=setenv bootargs ${bootargs} ip=dhcp mem=480M init=/init wvga calibration\0" \
162 "bootcmd=run bootcmd_android\0" \
163 "bootcmd_net=run bootargs_base bootargs_nfs; " \
164 "tftpboot ${loadaddr} ${kernel}; bootm\0" \
165 "bootcmd_android=run bootargs_base bootargs_android; " \
166 "mmcinit;cp.b 0x100000 ${loadaddr} 0x250000; " \
167 "cp.b 0x400000 ${rd_loadaddr} 0x4B000; " \
168 "bootm ${loadaddr} ${rd_loadaddr}\0" \
169 "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
170 "protect off ${uboot_addr} 0xa003ffff; " \
171 "erase ${uboot_addr} 0xa003ffff; " \
172 "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
173 "setenv filesize; saveenv\0"
177 #define CONFIG_SMC911X 1
178 #define CONFIG_SMC911X_16_BIT 1
179 #define CONFIG_SMC911X_BASE mx51_io_base_addr
183 * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under
184 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
185 * controller inverted. The controller is capable of detecting and correcting
186 * this, but it needs 4 network packets for that. Which means, at startup, you
187 * will not receive answers to the first 4 packest, unless there have been some
188 * broadcasts on the network, or your board is on a hub. Reducing the ARP
189 * timeout from default 5 seconds to 200ms we speed up the initial TFTP
190 * transfer, should the user wish one, significantly.
192 #define CONFIG_ARP_TIMEOUT 200UL
195 * Miscellaneous configurable options
197 #define CONFIG_SYS_LONGHELP /* undef to save memory */
198 #define CONFIG_SYS_PROMPT "BBG U-Boot > "
199 #define CONFIG_AUTO_COMPLETE
200 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
201 /* Print Buffer Size */
202 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
203 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
204 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
206 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
207 #define CONFIG_SYS_MEMTEST_END 0x10000
209 #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
211 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
213 #define CONFIG_SYS_HZ 1000
215 #define CONFIG_CMDLINE_EDITING 1
220 #define CONFIG_HAS_ETH1
221 #define CONFIG_NET_MULTI 1
222 #define CONFIG_MXC_FEC
224 #define CONFIG_DISCOVER_PHY
226 #define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
227 #define CONFIG_FEC0_PINMUX -1
228 #define CONFIG_FEC0_PHY_ADDR 0x1F
229 #define CONFIG_FEC0_MIIBASE -1
234 #define CONFIG_FSL_SF 1
235 #define CONFIG_CMD_SPI
236 #define CONFIG_CMD_SF
237 #define CONFIG_SPI_FLASH_IMX_ATMEL 1
238 #define CONFIG_SPI_FLASH_CS 1
239 #define CONFIG_IMX_ECSPI
240 #define CONFIG_IMX_SPI_PMIC
241 #define CONFIG_IMX_SPI_PMIC_CS 0
242 #define IMX_CSPI_VER_2_3 1
244 #define MAX_SPI_BYTES (64 * 4)
249 #ifdef CONFIG_CMD_MMC
251 #define CONFIG_GENERIC_MMC
252 #define CONFIG_IMX_MMC
253 #define CONFIG_SYS_FSL_ESDHC_NUM 2
254 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
255 #define CONFIG_SYS_MMC_ENV_DEV 0
256 #define CONFIG_DOS_PARTITION 1
257 #define CONFIG_CMD_FAT 1
258 #define CONFIG_CMD_EXT2 1
259 #define CONFIG_DYNAMIC_MMC_DEVNO
265 #define CONFIG_HARD_I2C 1
266 #define CONFIG_I2C_MXC 1
267 #define CONFIG_SYS_I2C_PORT I2C1_BASE_ADDR
268 #define CONFIG_SYS_I2C_SPEED 400000
269 #define CONFIG_SYS_I2C_SLAVE 0xfe
271 /*-----------------------------------------------------------------------
274 * The stack sizes are set up in start.S using the settings below
276 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
278 /*-----------------------------------------------------------------------
279 * Physical Memory Map
281 #define CONFIG_NR_DRAM_BANKS 1
282 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
283 #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
284 #define iomem_valid_addr(addr, size) \
285 (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
287 /*-----------------------------------------------------------------------
288 * FLASH and environment organization
290 #define CONFIG_SYS_NO_FLASH
292 /*-----------------------------------------------------------------------
293 * NAND FLASH driver setup
295 #define NAND_MAX_CHIPS 8
296 #define CONFIG_SYS_MAX_NAND_DEVICE 1
297 #define CONFIG_SYS_NAND_BASE 0x40000000
299 /* Monitor at beginning of flash */
300 /* #define CONFIG_FSL_ENV_IN_SF */
301 #define CONFIG_FSL_ENV_IN_MMC
302 /* #define CONFIG_FSL_ENV_IN_NAND */
304 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
305 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
307 #if defined(CONFIG_FSL_ENV_IN_NAND)
308 #define CONFIG_ENV_IS_IN_NAND 1
309 #define CONFIG_ENV_OFFSET 0x100000
310 #elif defined(CONFIG_FSL_ENV_IN_MMC)
311 #define CONFIG_ENV_IS_IN_MMC 1
312 #define CONFIG_ENV_OFFSET (768 * 1024)
313 #elif defined(CONFIG_FSL_ENV_IN_SF)
314 #define CONFIG_ENV_IS_IN_SPI_FLASH 1
315 #define CONFIG_ENV_SPI_CS 1
316 #define CONFIG_ENV_OFFSET (768 * 1024)
318 #define CONFIG_ENV_IS_NOWHERE 1
323 #undef CONFIG_JFFS2_CMDLINE
324 #define CONFIG_JFFS2_DEV "nand0"
326 #endif /* __CONFIG_H */