3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
8 /************************************************************************
9 * pcs440ep.h - configuration for PCS440EP board
10 ***********************************************************************/
15 /* new uImage format support */
17 #define CONFIG_OF_LIBFDT 1
18 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
20 /*-----------------------------------------------------------------------
21 * High Level Configuration Options
22 *----------------------------------------------------------------------*/
23 #define CONFIG_PCS440EP 1 /* Board is PCS440EP */
24 #define CONFIG_440EP 1 /* Specific PPC440EP support */
25 #define CONFIG_440 1 /* ... PPC440 family */
26 #define CONFIG_4xx 1 /* ... PPC4xx family */
28 #define CONFIG_SYS_TEXT_BASE 0xFFFA0000
30 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
32 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
33 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
35 /*-----------------------------------------------------------------------
36 * Base addresses -- Note these are effective addresses where the
37 * actual resources get mapped (not physical addresses)
38 *----------------------------------------------------------------------*/
39 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
40 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
41 #define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
42 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
43 #define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
44 #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
45 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
46 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
47 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
49 /*Don't change either of these*/
50 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
51 /*Don't change either of these*/
53 #define CONFIG_SYS_USB_DEVICE 0x50000000
54 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
56 /*-----------------------------------------------------------------------
57 * Initial RAM & stack pointer (placed in SDRAM)
58 *----------------------------------------------------------------------*/
59 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
60 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
61 #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
62 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
63 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
65 /*-----------------------------------------------------------------------
67 *----------------------------------------------------------------------*/
68 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
69 #define CONFIG_SYS_NS16550
70 #define CONFIG_SYS_NS16550_SERIAL
71 #define CONFIG_SYS_NS16550_REG_SIZE 1
72 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
73 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clk used */
74 #define CONFIG_BAUDRATE 115200
76 #define CONFIG_SYS_BAUDRATE_TABLE \
77 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
79 /*-----------------------------------------------------------------------
81 *----------------------------------------------------------------------*/
82 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
84 /*-----------------------------------------------------------------------
86 *----------------------------------------------------------------------*/
87 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
88 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
90 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
91 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
93 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
94 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
95 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
97 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
99 #ifdef CONFIG_ENV_IS_IN_FLASH
100 #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
101 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
102 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
104 #define CONFIG_ENV_OVERWRITE 1
106 /* Address and size of Redundant Environment Sector */
107 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
108 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
109 #endif /* CONFIG_ENV_IS_IN_FLASH */
111 #define ENV_NAME_REVLEV "revision_level"
112 #define ENV_NAME_SOLDER "solder_switch"
113 #define ENV_NAME_DIP "dip"
115 /*-----------------------------------------------------------------------
117 *----------------------------------------------------------------------*/
118 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
119 #undef CONFIG_DDR_ECC /* don't use ECC */
120 #define SPD_EEPROM_ADDRESS {0x50}
121 #define CONFIG_PROG_SDRAM_TLB 1
123 /*-----------------------------------------------------------------------
125 *----------------------------------------------------------------------*/
126 #define CONFIG_SYS_I2C
127 #define CONFIG_SYS_I2C_PPC4XX
128 #define CONFIG_SYS_I2C_PPC4XX_CH0
129 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
130 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
132 #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa4>>1)
133 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
134 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
135 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
137 #define CONFIG_PREBOOT "echo;" \
138 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
141 #undef CONFIG_BOOTARGS
143 #define CONFIG_EXTRA_ENV_SETTINGS \
145 "hostname=pcs440ep\0" \
146 "use_eeprom_ethaddr=default\0" \
148 "nfsargs=setenv bootargs root=/dev/nfs rw " \
149 "nfsroot=${serverip}:${rootpath}\0" \
150 "ramargs=setenv bootargs root=/dev/ram rw\0" \
151 "addip=setenv bootargs ${bootargs} " \
152 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
153 ":${hostname}:${netdev}:off panic=1\0" \
154 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
155 "flash_nfs=run nfsargs addip addtty;" \
156 "bootm ${kernel_addr}\0" \
157 "flash_self=run ramargs addip addtty;" \
158 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
159 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
161 "rootpath=/opt/eldk/ppc_4xx\0" \
162 "bootfile=/tftpboot/pcs440ep/uImage\0" \
163 "kernel_addr=FFF00000\0" \
164 "ramdisk_addr=FFF00000\0" \
165 "load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0" \
166 "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
167 "cp.b 100000 FFFA0000 60000\0" \
168 "upd=run load update\0" \
170 #define CONFIG_BOOTCOMMAND "run flash_self"
173 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
175 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
178 /* check U-Boot image with SHA1 sum */
179 #define CONFIG_SHA1_CHECK_UB_IMG 1
180 #define CONFIG_SHA1_START CONFIG_SYS_MONITOR_BASE
181 #define CONFIG_SHA1_LEN CONFIG_SYS_MONITOR_LEN
183 /*-----------------------------------------------------------------------
184 * Definitions for status LED
186 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
187 #define CONFIG_BOARD_SPECIFIC_LED 1
189 #define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */
190 #define STATUS_LED_PERIOD ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
191 #define STATUS_LED_STATE STATUS_LED_OFF
192 #define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */
193 #define STATUS_LED_PERIOD1 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
194 #define STATUS_LED_STATE1 STATUS_LED_ON
195 #define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */
196 #define STATUS_LED_PERIOD2 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
197 #define STATUS_LED_STATE2 STATUS_LED_OFF
198 #define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */
199 #define STATUS_LED_PERIOD3 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
200 #define STATUS_LED_STATE3 STATUS_LED_OFF
202 #define CONFIG_SHOW_BOOT_PROGRESS 1
204 #define CONFIG_BAUDRATE 115200
206 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
207 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
209 #define CONFIG_PPC4xx_EMAC
210 #define CONFIG_MII 1 /* MII PHY management */
211 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
212 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
213 #define CONFIG_PHY1_ADDR 2
215 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
217 #define CONFIG_NETCONSOLE /* include NetConsole support */
220 #define CONFIG_MAC_PARTITION
221 #define CONFIG_DOS_PARTITION
222 #define CONFIG_ISO_PARTITION
226 #define CONFIG_USB_OHCI
227 #define CONFIG_USB_STORAGE
229 /*Comment this out to enable USB 1.1 device*/
230 #define USB_2_0_DEVICE
231 #endif /*CONFIG_440EP*/
234 #define CONFIG_PANIC_HANG
236 #define CONFIG_HW_WATCHDOG /* watchdog */
243 #define CONFIG_BOOTP_BOOTFILESIZE
244 #define CONFIG_BOOTP_BOOTPATH
245 #define CONFIG_BOOTP_GATEWAY
246 #define CONFIG_BOOTP_HOSTNAME
250 * Command line configuration.
252 #include <config_cmd_default.h>
253 #define CONFIG_CMD_ASKENV
254 #define CONFIG_CMD_DHCP
255 #define CONFIG_CMD_DIAG
256 #define CONFIG_CMD_EEPROM
257 #define CONFIG_CMD_ELF
258 #define CONFIG_CMD_EXT2
259 #define CONFIG_CMD_FAT
260 #define CONFIG_CMD_I2C
261 #define CONFIG_CMD_IDE
262 #define CONFIG_CMD_IRQ
263 #define CONFIG_CMD_MII
264 #define CONFIG_CMD_NET
265 #define CONFIG_CMD_NFS
266 #define CONFIG_CMD_PCI
267 #define CONFIG_CMD_PING
268 #define CONFIG_CMD_REGINFO
269 #define CONFIG_CMD_REISER
270 #define CONFIG_CMD_SDRAM
271 #define CONFIG_CMD_USB
273 #define CONFIG_SUPPORT_VFAT
276 * Miscellaneous configurable options
278 #define CONFIG_SYS_LONGHELP /* undef to save memory */
279 #if defined(CONFIG_CMD_KGDB)
280 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
282 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
284 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
285 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
286 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
288 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
289 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
291 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
292 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
293 #define CONFIG_LYNXKDI 1 /* support kdi files */
295 /*-----------------------------------------------------------------------
297 *-----------------------------------------------------------------------
300 #define CONFIG_PCI /* include pci support */
301 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
302 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
303 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
304 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
306 /* Board-specific PCI */
307 #define CONFIG_SYS_PCI_TARGET_INIT
308 #define CONFIG_SYS_PCI_MASTER_INIT
310 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
311 #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
314 * For booting Linux, the board info and command line data
315 * have to be in the first 8 MB of memory, since this is
316 * the maximum mapped by the Linux kernel during initialization.
318 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
320 /*-----------------------------------------------------------------------
321 * External Bus Controller (EBC) Setup
322 *----------------------------------------------------------------------*/
323 #define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
324 #define FLASH_BASE1_PRELIM 0xFFF80000 /* FLASH bank #1 */
326 #define CONFIG_SYS_FLASH FLASH_BASE0_PRELIM
327 #define CONFIG_SYS_SRAM 0xF1000000
328 #define CONFIG_SYS_FPGA 0xF2000000
329 #define CONFIG_SYS_CF1 0xF0000000
330 #define CONFIG_SYS_CF2 0xF0100000
332 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
333 #define CONFIG_SYS_EBC_PB0AP 0x02010000 /* TWT=4,OEN=1 */
334 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
336 /* Memory Bank 1 (SRAM) initialization */
337 #define CONFIG_SYS_EBC_PB1AP 0x01810040 /* TWT=3,OEN=1,BEM=1 */
338 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */
340 /* Memory Bank 2 (FPGA) initialization */
341 #define CONFIG_SYS_EBC_PB2AP 0x01010440 /* TWT=2,OEN=1,TH=2,BEM=1 */
342 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */
344 /* Memory Bank 3 (CompactFlash) initialization */
345 #define CONFIG_SYS_EBC_PB3AP 0x080BD400
346 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
348 /* Memory Bank 4 (CompactFlash) initialization */
349 #define CONFIG_SYS_EBC_PB4AP 0x080BD400
350 #define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
352 /*-----------------------------------------------------------------------
353 * PPC440 GPIO Configuration
355 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
358 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
359 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
360 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
361 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
362 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
363 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
364 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \
365 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \
366 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \
367 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \
368 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \
369 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \
370 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \
371 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \
372 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \
373 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \
374 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \
375 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \
376 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \
377 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \
378 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \
379 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \
380 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \
381 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \
382 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \
383 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \
384 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \
385 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
386 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \
387 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
388 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
389 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
393 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \
394 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \
395 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
396 {GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
397 {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
398 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \
399 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
400 {GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \
401 {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \
402 {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \
403 {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \
404 {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \
405 {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
406 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
407 {GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
408 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
409 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
410 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \
411 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \
412 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \
413 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \
414 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \
415 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \
416 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \
417 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \
418 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \
419 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \
420 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \
421 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \
422 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \
423 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \
424 {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \
428 #if defined(CONFIG_CMD_KGDB)
429 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
432 /*-----------------------------------------------------------------------
433 * IDE/ATA stuff Supports IDE harddisk
434 *-----------------------------------------------------------------------
437 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
439 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
440 #undef CONFIG_IDE_LED /* LED for ide not supported */
442 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
443 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
445 #define CONFIG_IDE_PREINIT 1
446 #define CONFIG_IDE_RESET 1
448 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
450 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF1
452 /* Offset for data I/O */
453 #define CONFIG_SYS_ATA_DATA_OFFSET 0
455 /* Offset for normal register accesses */
456 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
458 /* Offset for alternate registers */
459 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0000)
461 #endif /* __CONFIG_H */