include/configs/pm9263.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  * Ilko Iliev <www.ronetix.at>
   6  *
   7  * Configuation settings for the RONETIX PM9263 board.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /* ARM asynchronous clock */
  32 #define CONFIG_DISPLAY_CPUINFO
  33 #define CONFIG_DISPLAY_BOARDINFO
  34
  35 #define MASTER_PLL_DIV          15
  36 #define MASTER_PLL_MUL          162
  37 #define MAIN_PLL_DIV            2       /* 2 or 4 */
  38 #define AT91_MAIN_CLOCK 18432000
  39
  40 #define CONFIG_SYS_HZ           1000
  41
  42 #define CONFIG_ARM926EJS        1       /* This is an ARM926EJS Core    */
  43 #define CONFIG_AT91SAM9263      1       /* It's an Atmel AT91SAM9263 SoC*/
  44 #define CONFIG_PM9263           1       /* on a Ronetix PM9263 Board    */
  45 #define CONFIG_ARCH_CPU_INIT
  46 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff  */
  47
  48 /* clocks */
  49 #define CONFIG_SYS_MOR_VAL      0x00002001      /* CKGR_MOR - enable main osc. */
  50 #define CONFIG_SYS_PLLAR_VAL    \
  51                 (0x2000BF00 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  52
  53 #if (MAIN_PLL_DIV == 2)
  54 /* PCK/2 = MCK Master Clock from PLLA */
  55 #define CONFIG_SYS_MCKR1_VAL            0x00000100
  56 /* PCK/2 = MCK Master Clock from PLLA */
  57 #define CONFIG_SYS_MCKR2_VAL            0x00000102
  58 #else
  59 /* PCK/4 = MCK Master Clock from PLLA */
  60 #define CONFIG_SYS_MCKR1_VAL            0x00000200
  61 /* PCK/4 = MCK Master Clock from PLLA */
  62 #define CONFIG_SYS_MCKR2_VAL            0x00000202
  63 #endif
  64 /* define PDC[31:16] as DATA[31:16] */
  65 #define CONFIG_SYS_PIOD_PDR_VAL1        0xFFFF0000
  66 /* no pull-up for D[31:16] */
  67 #define CONFIG_SYS_PIOD_PPUDR_VAL       0xFFFF0000
  68 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
  69 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL   0x0001010A
  70 /* EBI1_CSA, 3.3v, no pull-ups */
  71 #define CONFIG_SYS_MATRIX_EBI1CSA_VAL   0x00010100
  72
  73 /* SDRAM */
  74 /* SDRAMC_MR Mode register */
  75 #define CONFIG_SYS_SDRC_MR_VAL1         0
  76 /* SDRAMC_TR - Refresh Timer register */
  77 #define CONFIG_SYS_SDRC_TR_VAL1         0x13C
  78 #define CONFIG_SYS_SDRC_CR_VAL          0x85227279      /*CL3*/
  79 /* Memory Device Register -> SDRAM */
  80 #define CONFIG_SYS_SDRC_MDR_VAL         0
  81 #define CONFIG_SYS_SDRC_MR_VAL2         0x00000002      /* SDRAMC_MR */
  82 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
  83 #define CONFIG_SYS_SDRC_MR_VAL3         4               /* SDRC_MR */
  84 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
  85 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
  86 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
  87 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
  88 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
  89 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
  90 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
  91 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
  92 #define CONFIG_SYS_SDRC_MR_VAL4         3               /* SDRC_MR */
  93 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
  94 #define CONFIG_SYS_SDRC_MR_VAL5         0               /* SDRC_MR */
  95 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
  96 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
  97 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
  98
  99 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
 100 #define CONFIG_SYS_SMC0_SETUP0_VAL      0x0A0A0A0A      /* SMC_SETUP */
 101 #define CONFIG_SYS_SMC0_PULSE0_VAL      0x0B0B0B0B      /* SMC_PULSE */
 102 #define CONFIG_SYS_SMC0_CYCLE0_VAL      0x00160016      /* SMC_CYCLE */
 103 #define CONFIG_SYS_SMC0_CTRL0_VAL       0x00161003      /* SMC_MODE */
 104
 105 /* setup SMC1, CS0 (PSRAM) - 16-bit */
 106 #define CONFIG_SYS_SMC1_SETUP0_VAL      0x00000000      /* SMC_SETUP */
 107 #define CONFIG_SYS_SMC1_PULSE0_VAL      0x07020707      /* SMC_PULSE */
 108 #define CONFIG_SYS_SMC1_CYCLE0_VAL      0x00080008      /* SMC_CYCLE */
 109 #define CONFIG_SYS_SMC1_CTRL0_VAL       0x31001000      /* SMC_MODE */
 110
 111 #define CONFIG_SYS_RSTC_RMR_VAL         0xA5000301      /* user reset enable */
 112
 113 /* Watchdog */
 114 #define CONFIG_SYS_WDTC_WDMR_VAL        0x3fff8fff      /* disable watchdog */
 115
 116 /* */
 117
 118 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
 119 #define CONFIG_SETUP_MEMORY_TAGS 1
 120 #define CONFIG_INITRD_TAG       1
 121
 122 #undef CONFIG_SKIP_LOWLEVEL_INIT
 123 #undef CONFIG_SKIP_RELOCATE_UBOOT
 124 #define CONFIG_USER_LOWLEVEL_INIT       1
 125
 126 /*
 127  * Hardware drivers
 128  */
 129 #define CONFIG_ATMEL_USART      1
 130 #undef CONFIG_USART0
 131 #undef CONFIG_USART1
 132 #undef CONFIG_USART2
 133 #define CONFIG_USART3           1       /* USART 3 is DBGU */
 134
 135 /* LCD */
 136 #define CONFIG_LCD                      1
 137 #define LCD_BPP                         LCD_COLOR8
 138 #define CONFIG_LCD_LOGO                 1
 139 #undef LCD_TEST_PATTERN
 140 #define CONFIG_LCD_INFO                 1
 141 #define CONFIG_LCD_INFO_BELOW_LOGO      1
 142 #define CONFIG_SYS_WHITE_ON_BLACK       1
 143 #define CONFIG_ATMEL_LCD                1
 144 #define CONFIG_ATMEL_LCD_BGR555         1
 145 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
 146
 147 #define CONFIG_LCD_IN_PSRAM             1
 148
 149 /* LED */
 150 #define CONFIG_AT91_LED
 151 #define CONFIG_RED_LED          AT91_PIN_PB7    /* this is the power led */
 152 #define CONFIG_GREEN_LED        AT91_PIN_PB8    /* this is the user1 led */
 153
 154 #define CONFIG_BOOTDELAY        3
 155
 156 /*
 157  * BOOTP options
 158  */
 159 #define CONFIG_BOOTP_BOOTFILESIZE       1
 160 #define CONFIG_BOOTP_BOOTPATH           1
 161 #define CONFIG_BOOTP_GATEWAY            1
 162 #define CONFIG_BOOTP_HOSTNAME           1
 163
 164 /*
 165  * Command line configuration.
 166  */
 167 #include <config_cmd_default.h>
 168 #undef CONFIG_CMD_BDI
 169 #undef CONFIG_CMD_IMI
 170 #undef CONFIG_CMD_AUTOSCRIPT
 171 #undef CONFIG_CMD_FPGA
 172 #undef CONFIG_CMD_LOADS
 173 #undef CONFIG_CMD_IMLS
 174
 175 #define CONFIG_CMD_PING         1
 176 #define CONFIG_CMD_DHCP         1
 177 #define CONFIG_CMD_NAND         1
 178 #define CONFIG_CMD_USB          1
 179
 180 /* SDRAM */
 181 #define CONFIG_NR_DRAM_BANKS    1
 182 #define PHYS_SDRAM              0x20000000
 183 #define PHYS_SDRAM_SIZE         0x04000000      /* 64 megs */
 184
 185 /* DataFlash */
 186 #define CONFIG_ATMEL_DATAFLASH_SPI
 187 #define CONFIG_HAS_DATAFLASH                    1
 188 #define CONFIG_SYS_SPI_WRITE_TOUT               (5 * CONFIG_SYS_HZ)
 189 #define CONFIG_SYS_MAX_DATAFLASH_BANKS          1
 190 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000      /* CS0 */
 191 #define AT91_SPI_CLK                            15000000
 192 #define DATAFLASH_TCSS                          (0x1a << 16)
 193 #define DATAFLASH_TCHS                          (0x1 << 24)
 194
 195 /* NOR flash, if populated */
 196 #define CONFIG_SYS_FLASH_CFI            1
 197 #define CONFIG_FLASH_CFI_DRIVER         1
 198 #define PHYS_FLASH_1                    0x10000000
 199 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 200 #define CONFIG_SYS_MAX_FLASH_SECT       256
 201 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 202
 203 /* NAND flash */
 204 #ifdef CONFIG_CMD_NAND
 205 #define CONFIG_NAND_ATMEL
 206 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 207 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 208 #define CONFIG_SYS_NAND_BASE            0x40000000
 209 #define CONFIG_SYS_NAND_DBW_8           1
 210 /* our ALE is AD21 */
 211 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
 212 /* our CLE is AD22 */
 213 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
 214 #define CONFIG_SYS_NAND_ENABLE_PIN      AT91_PIN_PD15
 215 #define CONFIG_SYS_NAND_READY_PIN       AT91_PIN_PB30
 216 #endif
 217
 218 #define CONFIG_CMD_JFFS2                1
 219 #define CONFIG_JFFS2_CMDLINE            1
 220 #define CONFIG_JFFS2_NAND               1
 221 #define CONFIG_JFFS2_DEV                "nand0" /* NAND device jffs2 lives on */
 222 #define CONFIG_JFFS2_PART_OFFSET        0       /* start of jffs2 partition */
 223 #define CONFIG_JFFS2_PART_SIZE          (256 * 1024 * 1024) /* partition size*/
 224
 225 /* PSRAM */
 226 #define PHYS_PSRAM                      0x70000000
 227 #define PHYS_PSRAM_SIZE                 0x00400000      /* 4MB */
 228
 229 /* Ethernet */
 230 #define CONFIG_MACB                     1
 231 #define CONFIG_RMII                     1
 232 #define CONFIG_NET_MULTI                1
 233 #define CONFIG_NET_RETRY_COUNT          20
 234 #define CONFIG_RESET_PHY_R              1
 235
 236 /* USB */
 237 #define CONFIG_USB_ATMEL
 238 #define CONFIG_USB_OHCI_NEW                     1
 239 #define CONFIG_DOS_PARTITION                    1
 240 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
 241 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00a00000      /* AT91SAM9263_UHP_BASE */
 242 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9263"
 243 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 244 #define CONFIG_USB_STORAGE                      1
 245
 246 #define CONFIG_SYS_LOAD_ADDR                    0x22000000      /* load address */
 247
 248 #define CONFIG_SYS_MEMTEST_START                PHYS_SDRAM
 249 #define CONFIG_SYS_MEMTEST_END                  0x23e00000
 250
 251 #define CONFIG_SYS_USE_FLASH    1
 252 #undef CONFIG_SYS_USE_DATAFLASH
 253 #undef CONFIG_SYS_USE_NANDFLASH
 254
 255 #ifdef CONFIG_SYS_USE_DATAFLASH
 256
 257 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 258 #define CONFIG_ENV_IS_IN_DATAFLASH
 259 #define CFG_MONITOR_BASE        (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
 260 #define CONFIG_ENV_OFFSET       0x4200
 261 #define CONFIG_ENV_ADDR         (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 262 #define CONFIG_ENV_SIZE         0x4200
 263 #define CONFIG_BOOTCOMMAND      "cp.b 0xC0042000 0x22000000 0x210000; bootm"
 264 #define CONFIG_BOOTARGS         "console=ttyS0,115200 " \
 265                                 "root=/dev/mtdblock0 " \
 266                                 "mtdparts=at91_nand:-(root) "\
 267                                 "rw rootfstype=jffs2"
 268
 269 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
 270
 271 /* bootstrap + u-boot + env + linux in nandflash */
 272 #define CONFIG_ENV_IS_IN_NAND
 273 #define CONFIG_ENV_OFFSET               0x60000
 274 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 275 #define CONFIG_ENV_SIZE         0x20000         /* 1 sector = 128 kB */
 276 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0xA0000 0x200000; bootm"
 277 #define CONFIG_BOOTARGS         "console=ttyS0,115200 "         \
 278                                 "root=/dev/mtdblock5 "          \
 279                                 "mtdparts=at91_nand:"           \
 280                                         "128k(bootstrap)ro,"    \
 281                                         "256k(uboot)ro,"        \
 282                                         "128k(env1)ro,"         \
 283                                         "128k(env2)ro,"         \
 284                                         "2M(linux),"            \
 285                                         "-(root) "              \
 286                                 "rw rootfstype=jffs2"
 287
 288 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
 289
 290 #define CONFIG_ENV_IS_IN_FLASH  1
 291 #define CONFIG_ENV_OFFSET       0x40000
 292 #define CONFIG_ENV_SECT_SIZE    0x10000
 293 #define CONFIG_ENV_SIZE         0x10000
 294 #define CONFIG_ENV_OVERWRITE    1
 295
 296 /* JFFS Partition offset set */
 297 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 298 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 299
 300 /* 512k reserved for u-boot */
 301 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   11
 302
 303 #define CONFIG_BOOTCOMMAND              "run flashboot"
 304 #define CONFIG_ROOTPATH                 /ronetix/rootfs
 305 #define CONFIG_AUTOBOOT_PROMPT          "autoboot in %d seconds\n"
 306
 307 #define CONFIG_CON_ROT                  "fbcon=rotate:3 "
 308 #define CONFIG_BOOTARGS                 "root=/dev/mtdblock4 rootfstype=jffs2 "\
 309                                         CONFIG_CON_ROT
 310
 311 #define MTDIDS_DEFAULT                  "nor0=physmap-flash.0,nand0=nand"
 312 #define MTDPARTS_DEFAULT                \
 313         "mtdparts=physmap-flash.0:"     \
 314                 "256k(u-boot)ro,"       \
 315                 "64k(u-boot-env)ro,"    \
 316                 "1408k(kernel),"        \
 317                 "-(rootfs);"            \
 318         "nand:-(nand)"
 319
 320 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 321         "mtdids=" MTDIDS_DEFAULT "\0"                           \
 322         "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
 323         "partition=nand0,0\0"                                   \
 324         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
 325         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
 326                 CONFIG_CON_ROT                                  \
 327                 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
 328         "addip=setenv bootargs $(bootargs) "                    \
 329                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
 330                 ":$(hostname):eth0:off\0"                       \
 331         "ramboot=tftpboot 0x22000000 vmImage;"                  \
 332                 "run ramargs;run addip;bootm 22000000\0"        \
 333         "nfsboot=tftpboot 0x22000000 vmImage;"                  \
 334                 "run nfsargs;run addip;bootm 22000000\0"        \
 335         "flashboot=run ramargs;run addip;bootm 0x10050000\0"    \
 336         ""
 337
 338 #else
 339 #error "Undefined memory device"
 340 #endif
 341
 342 #define CONFIG_BAUDRATE                 115200
 343 #define CONFIG_SYS_BAUDRATE_TABLE       {115200 , 19200, 38400, 57600, 9600 }
 344
 345 #define CONFIG_SYS_PROMPT               "u-boot-pm9263> "
 346 #define CONFIG_SYS_CBSIZE               256
 347 #define CONFIG_SYS_MAXARGS              16
 348 #define CONFIG_SYS_PBSIZE               \
 349                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 350 #define CONFIG_SYS_LONGHELP             1
 351 #define CONFIG_CMDLINE_EDITING          1
 352
 353 #define ROUND(A, B)                     (((A) + (B)) & ~((B) - 1))
 354 /*
 355  * Size of malloc() pool
 356  */
 357 #define CONFIG_SYS_MALLOC_LEN   ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
 358 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* 128 bytes for initial data */
 359
 360 #define CONFIG_STACKSIZE                (32 * 1024)     /* regular stack */
 361
 362 #ifdef CONFIG_USE_IRQ
 363 #error CONFIG_USE_IRQ not supported
 364 #endif
 365
 366 #endif