2 * Copyright (C) ST-Ericsson SA 2009
4 * SPDX-License-Identifier: GPL-2.0+
14 #define CONFIG_SKIP_LOWLEVEL_INIT
15 #define CONFIG_SNOWBALL
16 #define CONFIG_SYS_ICACHE_OFF
17 #define CONFIG_SYS_DCACHE_OFF
18 #define CONFIG_ARCH_CPU_INIT
19 #define CONFIG_BOARD_LATE_INIT
22 * High Level Configuration Options
28 #define CONFIG_SYS_MEMTEST_START 0x00000000
29 #define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF
30 #define CONFIG_SYS_HZ 1000 /* must be 1000 */
32 /*-----------------------------------------------------------------------
33 * Size of environment and malloc() pool
36 * If you use U-Boot as crash kernel, make sure that it does not overwrite
37 * information saved by kexec during panic. Kexec expects the start
38 * address of the executable 32K above "crashkernel" address.
41 * Size of malloc() pool
43 #define CONFIG_ENV_SIZE (8*1024)
44 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
46 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
48 #define CONFIG_ENV_IS_IN_MMC
49 #define CONFIG_CMD_ENV
50 #define CONFIG_CMD_SAVEENV
51 #define CONFIG_ENV_OFFSET 0x0118000
52 #define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */
57 #define CONFIG_PL011_SERIAL
58 #define CONFIG_PL011_SERIAL_RLCR
59 #define CONFIG_PL011_SERIAL_FLUSH_ON_INIT
62 * U8500 UART registers base for 3 serial devices
64 #define CFG_UART0_BASE 0x80120000
65 #define CFG_UART1_BASE 0x80121000
66 #define CFG_UART2_BASE 0x80007000
67 #define CFG_SERIAL0 CFG_UART0_BASE
68 #define CFG_SERIAL1 CFG_UART1_BASE
69 #define CFG_SERIAL2 CFG_UART2_BASE
70 #define CONFIG_PL011_CLOCK 38400000
71 #define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
73 #define CONFIG_CONS_INDEX 2
74 #define CONFIG_BAUDRATE 115200
77 * Devices and file systems
80 #define CONFIG_GENERIC_MMC
81 #define CONFIG_DOS_PARTITION
86 #define CONFIG_CMD_MEMORY
87 #define CONFIG_CMD_BOOTD
88 #define CONFIG_CMD_BDI
89 #define CONFIG_CMD_IMI
90 #define CONFIG_CMD_MISC
91 #define CONFIG_CMD_RUN
92 #define CONFIG_CMD_ECHO
93 #define CONFIG_CMD_CONSOLE
94 #define CONFIG_CMD_LOADS
95 #define CONFIG_CMD_LOADB
96 #define CONFIG_CMD_MMC
97 #define CONFIG_CMD_FAT
98 #define CONFIG_CMD_EXT2
99 #define CONFIG_CMD_SOURCE
101 #ifndef CONFIG_BOOTDELAY
102 #define CONFIG_BOOTDELAY 1
104 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
106 #undef CONFIG_BOOTARGS
107 #define CONFIG_BOOTCOMMAND \
109 "if run loadbootscript; " \
110 "then run bootscript; " \
113 "then run mmcboot; " \
116 "if run emmcloadbootscript; " \
117 "then run bootscript; " \
119 "if run emmcload; " \
120 "then run emmcboot; " \
122 "echo No media to boot from; " \
128 #define CONFIG_EXTRA_ENV_SETTINGS \
130 "loadaddr=0x00100000\0" \
131 "console=ttyAMA2,115200n8\0" \
132 "loadbootscript=fatload mmc 1:1 ${loadaddr} boot.scr\0" \
133 "emmcloadbootscript=fatload mmc 0:2 ${loadaddr} boot.scr\0" \
134 "bootscript=echo Running bootscript " \
135 "from mmc ...; source ${loadaddr}\0" \
136 "memargs256=mem=96M@0 mem_modem=32M@96M mem=32M@128M " \
137 "hwmem=22M@160M pmem_hwb=42M@182M mem_mali=32@224M\0" \
138 "memargs512=mem=96M@0 mem_modem=32M@96M hwmem=32M@128M " \
139 "mem=64M@160M mem_mali=32M@224M " \
140 "pmem_hwb=128M@256M mem=128M@384M\0" \
141 "memargs1024=mem=128M@0 mali.mali_mem=32M@128M " \
142 "hwmem=168M@M160M mem=48M@328M " \
143 "mem_issw=1M@383M mem=640M@384M\0" \
144 "memargs=setenv bootargs ${bootargs} ${memargs1024}\0" \
145 "emmcload=fatload mmc 0:2 ${loadaddr} uImage\0" \
146 "mmcload=fatload mmc 1:1 ${loadaddr} uImage\0" \
147 "commonargs=setenv bootargs console=${console} " \
149 "emmcargs=setenv bootargs ${bootargs} " \
150 "root=/dev/mmcblk0p3 " \
152 "addcons=setenv bootargs ${bootargs} " \
153 "console=${console}\0" \
154 "emmcboot=echo Booting from eMMC ...; " \
155 "run commonargs emmcargs memargs; " \
156 "bootm ${loadaddr}\0" \
157 "mmcargs=setenv bootargs ${bootargs} " \
158 "root=/dev/mmcblk1p2 " \
159 "rootwait earlyprintk\0" \
160 "mmcboot=echo Booting from external MMC ...; " \
161 "run commonargs mmcargs memargs; " \
162 "bootm ${loadaddr}\0" \
163 "fdt_high=0x2BC00000\0" \
164 "stdout=serial,usbtty\0" \
165 "stdin=serial,usbtty\0" \
166 "stderr=serial,usbtty\0"
168 /*-----------------------------------------------------------------------
169 * Miscellaneous configurable options
172 #define CONFIG_SYS_LONGHELP /* undef to save memory */
173 #define CONFIG_SYS_PROMPT "U8500 $ " /* Monitor Command Prompt */
174 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
176 /* Print Buffer Size */
177 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
178 + sizeof(CONFIG_SYS_PROMPT) + 16)
179 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
180 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
182 #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
183 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
184 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1
186 #define CONFIG_SYS_HUSH_PARSER 1
187 #define CONFIG_CMDLINE_EDITING
189 #define CONFIG_SETUP_MEMORY_TAGS 2
190 #define CONFIG_INITRD_TAG 1
191 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
194 * Physical Memory Map
196 #define CONFIG_NR_DRAM_BANKS 1
197 #define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */
200 * additions for new relocation code
202 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
203 #define CONFIG_SYS_MAX_RAM_SIZE 0x40000000
204 #define CONFIG_SYS_INIT_RAM_SIZE 0x100000
205 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
206 CONFIG_SYS_INIT_RAM_SIZE - \
207 GENERATED_GBL_DATA_SIZE)
208 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
210 /* landing address before relocation */
211 #ifndef CONFIG_SYS_TEXT_BASE
212 #define CONFIG_SYS_TEXT_BASE 0x0
216 * MMC related configs
218 #define CONFIG_ARM_PL180_MMCI
219 #define MMC_BLOCK_SIZE 512
220 #define CFG_EMMC_BASE 0x80114000
221 #define CFG_MMC_BASE 0x80126000
224 * FLASH and environment organization
226 #define CONFIG_SYS_NO_FLASH
229 * base register values for U8500
231 #define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock */
235 * U8500 GPIO register base for 9 banks
237 #define CONFIG_DB8500_GPIO
238 #define CFG_GPIO_0_BASE 0x8012E000
239 #define CFG_GPIO_1_BASE 0x8012E080
240 #define CFG_GPIO_2_BASE 0x8000E000
241 #define CFG_GPIO_3_BASE 0x8000E080
242 #define CFG_GPIO_4_BASE 0x8000E100
243 #define CFG_GPIO_5_BASE 0x8000E180
244 #define CFG_GPIO_6_BASE 0x8011E000
245 #define CFG_GPIO_7_BASE 0x8011E080
246 #define CFG_GPIO_8_BASE 0xA03FE000
248 #define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
250 #endif /* __CONFIG_H */