2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/socfpga_base_addrs.h>
10 #include "../../board/altera/socfpga/pinmux_config.h"
11 #include "../../board/altera/socfpga/iocsr_config.h"
12 #include "../../board/altera/socfpga/pll_config.h"
15 * High level configuration
17 /* Virtual target or real hardware */
18 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
23 #define CONFIG_MISC_INIT_R
24 #define CONFIG_SINGLE_BOOTLOADER
25 #define CONFIG_SOCFPGA
28 #define CONFIG_SYS_ARM_CACHE_WRITEALLOC
29 #define CONFIG_SYS_CACHELINE_SIZE 32
31 /* base address for .text section */
32 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
33 #define CONFIG_SYS_TEXT_BASE 0x08000040
35 #define CONFIG_SYS_TEXT_BASE 0x01000040
37 #define CONFIG_SYS_LOAD_ADDR 0x7fc0
39 /* Console I/O Buffer Size */
40 #define CONFIG_SYS_CBSIZE 256
41 /* Monitor Command Prompt */
42 #define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
43 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
44 sizeof(CONFIG_SYS_PROMPT) + 16)
47 * Display CPU and Board Info
49 #define CONFIG_DISPLAY_CPUINFO
50 #define CONFIG_DISPLAY_BOARDINFO
53 * Enable early stage initialization at C environment
55 #define CONFIG_BOARD_EARLY_INIT_F
57 /* flat device tree */
58 #define CONFIG_OF_LIBFDT
59 /* skip updating the FDT blob */
60 #define CONFIG_FDT_BLOB_SKIP_UPDATE
61 /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
62 #define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
64 #define CONFIG_SPL_RAM_DEVICE
65 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
66 #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
67 #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
70 * Memory allocation (MALLOC)
72 /* Room required on the stack for the environment data */
73 #define CONFIG_ENV_SIZE 1024
74 /* Size of DRAM reserved for malloc() use */
75 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
77 /* SP location before relocation, must use scratch RAM */
78 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
79 /* Reserving 0x100 space at back of scratch RAM for debug info */
80 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
81 /* Stack pointer prior relocation, must situated at on-chip RAM */
82 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
83 CONFIG_SYS_INIT_RAM_SIZE - \
84 GENERATED_GBL_DATA_SIZE)
88 * Command line configuration.
90 #define CONFIG_SYS_NO_FLASH
91 #include <config_cmd_default.h>
92 /* FAT file system support */
93 #define CONFIG_CMD_FAT
99 #define CONFIG_DOS_PARTITION 1
101 #ifdef CONFIG_SPL_BUILD
102 #undef CONFIG_PARTITIONS
109 /* Delay before automatically booting the default image */
110 #define CONFIG_BOOTDELAY 3
111 /* Enable auto completion of commands using TAB */
112 #define CONFIG_AUTO_COMPLETE
113 /* use "hush" command parser */
114 #define CONFIG_SYS_HUSH_PARSER
115 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
116 #define CONFIG_CMD_RUN
118 #define CONFIG_BOOTCOMMAND "run ramboot"
121 * arguments passed to the bootm command. The value of
122 * CONFIG_BOOTARGS goes into the environment value "bootargs".
123 * Do note the value will overide also the chosen node in FDT blob.
125 #define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
127 #define CONFIG_EXTRA_ENV_SETTINGS \
129 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
130 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
131 "bootm ${loadaddr} - ${fdt_addr}\0" \
132 "bootimage=uImage\0" \
134 "fsloadcmd=ext2load\0" \
135 "bootm ${loadaddr} - ${fdt_addr}\0" \
136 "qspiroot=/dev/mtdblock0\0" \
137 "qspirootfstype=jffs2\0" \
138 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
139 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
140 "bootm ${loadaddr} - ${fdt_addr}\0"
142 /* using environment setting for stdin, stdout, stderr */
143 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
144 /* Enable the call to overwrite_console() */
145 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
146 /* Enable overwrite of previous console environment settings */
147 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
149 /* max number of command args */
150 #define CONFIG_SYS_MAXARGS 16
160 /* We have 1 bank of DRAM */
161 #define CONFIG_NR_DRAM_BANKS 1
163 #define CONFIG_SYS_SDRAM_BASE 0x00000000
164 /* SDRAM memory size */
165 #define PHYS_SDRAM_1_SIZE 0x40000000
167 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
168 #define CONFIG_SYS_MEMTEST_START 0x00000000
169 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
172 * NS16550 Configuration
174 #define UART0_BASE SOCFPGA_UART0_ADDRESS
175 #define CONFIG_SYS_NS16550
176 #define CONFIG_SYS_NS16550_SERIAL
177 #define CONFIG_SYS_NS16550_REG_SIZE -4
178 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
179 #define CONFIG_CONS_INDEX 1
180 #define CONFIG_SYS_NS16550_COM1 UART0_BASE
181 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
182 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
183 #define V_NS16550_CLK 1000000
185 #define V_NS16550_CLK 100000000
187 #define CONFIG_BAUDRATE 115200
192 #define CONFIG_SYS_NO_FLASH
197 /* This timer use eosc1 where the clock frequency is fixed
198 * throughout any condition */
199 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
201 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
202 #define CONFIG_SYS_TIMER_RATE 2400000
204 #define CONFIG_SYS_TIMER_RATE 25000000
206 #define CONFIG_SYS_TIMER_COUNTS_DOWN
207 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
209 #define CONFIG_ENV_IS_NOWHERE
214 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
215 #define CONFIG_DESIGNWARE_ETH 1
218 #ifdef CONFIG_DESIGNWARE_ETH
219 #define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS
220 #define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS
221 /* console support for network */
222 #define CONFIG_CMD_DHCP
223 #define CONFIG_CMD_MII
224 #define CONFIG_CMD_NET
225 #define CONFIG_CMD_PING
227 #define CONFIG_NET_MULTI
228 #define CONFIG_DW_ALTDESCRIPTOR
230 #define CONFIG_PHY_GIGE
231 #define CONFIG_DW_AUTONEG
232 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
233 #define CONFIG_PHYLIB
234 #define CONFIG_PHY_MICREL
235 #define CONFIG_PHY_MICREL_KSZ9021
236 /* EMAC controller and PHY used */
237 #define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE
238 #define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR
239 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
240 #endif /* CONFIG_DESIGNWARE_ETH */
245 #define CONFIG_HW_WATCHDOG
246 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
247 #define CONFIG_DESIGNWARE_WATCHDOG
248 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
249 /* Clocks source frequency to watchdog timer */
250 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
254 * SPL "Second Program Loader" aka Initial Software
257 /* Enable building of SPL globally */
258 #define CONFIG_SPL_FRAMEWORK
260 /* TEXT_BASE for linking the SPL binary */
261 #define CONFIG_SPL_TEXT_BASE 0xFFFF0000
263 /* Stack size for SPL */
264 #define CONFIG_SPL_STACK_SIZE (4 * 1024)
266 /* MALLOC size for SPL */
267 #define CONFIG_SPL_MALLOC_SIZE (5 * 1024)
269 #define CONFIG_SPL_SERIAL_SUPPORT
270 #define CONFIG_SPL_BOARD_INIT
272 #define CHUNKSZ_CRC32 (1 * 1024)
274 #define CONFIG_CRC32_VERIFY
276 /* Linker script for SPL */
277 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
279 /* Support for common/libcommon.o in SPL binary */
280 #define CONFIG_SPL_LIBCOMMON_SUPPORT
281 /* Support for lib/libgeneric.o in SPL binary */
282 #define CONFIG_SPL_LIBGENERIC_SUPPORT
284 /* Support for watchdog */
285 #define CONFIG_SPL_WATCHDOG_SUPPORT
287 #endif /* __CONFIG_H */