3 * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
5 * Configuation settings for the SPC1920 board.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #define CONFIG_SPC1920 1 /* SPC1920 board */
27 #define CONFIG_MPC885 1 /* MPC885 CPU */
29 #define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
30 #undef CONFIG_8xx_CONS_SMC2
31 #undef CONFIG_8xx_CONS_NONE
34 /* #define MII_DEBUG */
35 /* #define CONFIG_FEC_ENET */
36 #undef CONFIG_ETHER_ON_FEC1
37 #define CONFIG_ETHER_ON_FEC2
39 /* #define CONFIG_FEC2_PHY_NORXERR */
40 /* #define CFG_DISCOVER_PHY */
41 /* #define CONFIG_PHY_ADDR 0x1 */
42 #define CONFIG_FEC2_PHY 1
44 #define CONFIG_BAUDRATE 19200
46 /* use PLD CLK4 instead of brg */
47 #undef CFG_SPC1920_SMC1_CLK4
49 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
50 #define CONFIG_8xx_CPUCLK_DEFAULT 50000000
51 #define CFG_8xx_CPUCLK_MIN 40000000
52 #define CFG_8xx_CPUCLK_MAX 133000000
54 #define CFG_RESET_ADDRESS 0xf8000000
56 #define CONFIG_BOARD_EARLY_INIT_F
60 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
62 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
65 #define CONFIG_ENV_OVERWRITE
67 #define CONFIG_NFSBOOTCOMMAND \
69 "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
70 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
73 #define CONFIG_BOOTCOMMAND \
74 "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
75 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
78 #undef CONFIG_BOOTARGS
80 #undef CONFIG_WATCHDOG /* watchdog disabled */
81 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
83 #ifndef CONFIG_COMMANDS
84 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
93 /* & ~( CFG_CMD_NET)) */
96 #endif /* !CONFIG_COMMANDS */
98 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
99 #include <cmd_confdefs.h>
102 * Miscellaneous configurable options
104 #define CFG_LONGHELP /* undef to save memory */
105 #define CFG_PROMPT "=>" /* Monitor Command Prompt */
106 #define CFG_HUSH_PARSER
107 #define CFG_PROMPT_HUSH_PS2 "> "
109 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
110 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
112 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
115 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
116 #define CFG_MAXARGS 16 /* max number of command args */
117 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
119 #define CFG_LOAD_ADDR 0x00100000
121 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
123 #define CFG_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 }
126 * Low Level Configuration Settings
127 * (address mappings, register initial values, etc.)
128 * You should know what you are doing if you make changes here.
131 /*-----------------------------------------------------------------------
132 * Internal Memory Mapped Register
134 #define CFG_IMMR 0xF0000000
136 /*-----------------------------------------------------------------------
137 * Definitions for initial stack pointer and data area (in DPRAM)
139 #define CFG_INIT_RAM_ADDR CFG_IMMR
140 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
141 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
142 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
143 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
145 /*-----------------------------------------------------------------------
146 * Start addresses for the final memory configuration
147 * (Set up by the startup code)
148 * Please note that CFG_SDRAM_BASE _must_ start at 0
150 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
151 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
154 * For booting Linux, the board info and command line data
155 * have to be in the first 8 MB of memory, since this is
156 * the maximum mapped by the Linux kernel during initialization.
158 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
160 #define CFG_MONITOR_BASE TEXT_BASE
161 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
164 #define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
166 #define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
167 #endif /* CONFIG_BZIP2 */
169 #define CFG_ALLOC_DPRAM 1 /* use allocation routines */
174 /*-----------------------------------------------------------------------
177 #define CFG_FLASH_BASE 0xFE000000
178 #define CFG_FLASH_CFI /* The flash is CFI compatible */
179 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
180 #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
181 #define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
183 /* Environment is in flash */
184 #define CFG_ENV_IS_IN_FLASH
185 #define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
186 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
188 #define CONFIG_ENV_OVERWRITE
190 /*-----------------------------------------------------------------------
191 * Cache Configuration
193 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
194 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
196 /*-----------------------------------------------------------------------
199 #if (CONFIG_COMMANDS & CFG_CMD_I2C)
200 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
201 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
202 #define CFG_I2C_SLAVE 0x7F
205 /*-----------------------------------------------------------------------
206 * SYPCR - System Protection Control 11-9
207 * SYPCR can only be written once after reset!
208 *-----------------------------------------------------------------------
209 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
211 #if defined(CONFIG_WATCHDOG)
212 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
213 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
215 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
218 /*-----------------------------------------------------------------------
219 * SIUMCR - SIU Module Configuration 11-6
220 *-----------------------------------------------------------------------
221 * PCMCIA config., multi-function pin tri-state
223 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
225 /*-----------------------------------------------------------------------
226 * TBSCR - Time Base Status and Control 11-26
227 *-----------------------------------------------------------------------
228 * Clear Reference Interrupt Status, Timebase freezing enabled
230 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
232 /*-----------------------------------------------------------------------
233 * PISCR - Periodic Interrupt Status and Control 11-31
234 *-----------------------------------------------------------------------
235 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
237 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
239 /*-----------------------------------------------------------------------
240 * SCCR - System Clock and reset Control Register 15-27
241 *-----------------------------------------------------------------------
242 * Set clock output, timebase and RTC source and divider,
243 * power management and some other internal clocks
245 #define SCCR_MASK SCCR_EBDF11
246 /* #define CFG_SCCR SCCR_TBS */
247 #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
248 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
251 /*-----------------------------------------------------------------------
252 * DER - Debug Enable Register
253 *-----------------------------------------------------------------------
254 * Set to zero to prevent the processor from entering debug mode
259 /* Because of the way the 860 starts up and assigns CS0 the entire
260 * address space, we have to set the memory controller differently.
261 * Normally, you write the option register first, and then enable the
262 * chip select by writing the base register. For CS0, you must write
263 * the base register first, followed by the option register.
268 * Init Memory Controller:
271 /* BR0 and OR0 (FLASH) */
272 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
275 /* used to re-map FLASH both when starting from SRAM or FLASH:
276 * restrict access enough to keep SRAM working (if any)
277 * but not too much to meddle with FLASH accesses
279 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
280 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
285 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
286 OR_SCY_3_CLK | OR_EHTR | OR_BI)
288 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
289 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
290 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
296 #define CFG_SDRAM_BASE 0x00000000
297 #define CFG_SDRAM_BASE_PRELIM CFG_SDRAM_BASE
298 #define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */
300 #define CFG_PRELIM_OR1_AM 0xF0000000
301 /* #define CFG_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */
302 #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
304 #define CFG_OR1_PRELIM (CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
305 #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
307 /* #define CFG_OR1_FINAL ((CFG_OR1_AM & OR_AM_MSK) | CFG_OR1_TIMING) */
308 /* #define CFG_BR1_FINAL ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
310 #define CFG_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64))
311 #define CFG_PTA_PER_CLK 195
312 #define CFG_MBMR_PTB 195
313 #define CFG_MPTPR MPTPR_PTP_DIV16
316 #define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
322 MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
324 #define CFG_MBMR_9COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
330 MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
334 #define CFG_SPC1920_PLD_BASE 0x80000000
335 #define CFG_PRELIM_OR5_AM 0xffff8000
337 #define CFG_OR5_PRELIM (CFG_PRELIM_OR5_AM | \
344 #define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
346 /* #define CFG_PLD_BASE 0x30000000 */
347 /* #define CFG_OR5_PRELIM 0xffff1110 */
348 /* #define CFG_BR5_PRELIM 0x30000401 */
351 * Internal Definitions
355 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
356 #define BOOTFLAG_WARM 0x02 /* Software reboot */
360 #define _MACH_8xx (_MACH_fads)
362 #endif /* __CONFIG_H */