2 * Copyright (C) 2012 <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0
11 #define CONFIG_MX28 /* must be defined before including regs-base.h */
13 #include <asm/sizes.h>
14 #include <asm/arch/regs-base.h>
17 * Ka-Ro TX28 board - SoC configuration
19 #define CONFIG_MXS_GPIO /* GPIO control */
20 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
21 #define PHYS_SDRAM_1_SIZE CONFIG_SDRAM_SIZE
23 #define TX28_MOD_SUFFIX "1"
25 #define CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
26 #define TX28_MOD_SUFFIX "0"
29 #ifndef CONFIG_SPL_BUILD
30 #define CONFIG_SKIP_LOWLEVEL_INIT
31 #define CONFIG_SHOW_ACTIVITY
32 #define CONFIG_ARCH_CPU_INIT
33 #define CONFIG_DISPLAY_CPUINFO
34 #define CONFIG_DISPLAY_BOARDINFO
35 #define CONFIG_BOARD_LATE_INIT
36 #define CONFIG_BOARD_EARLY_INIT_F
38 /* LCD Logo and Splash screen support */
41 #define CONFIG_SPLASH_SCREEN
42 #define CONFIG_SPLASH_SCREEN_ALIGN
43 #define CONFIG_VIDEO_MXS
44 #define CONFIG_LCD_LOGO
45 #define LCD_BPP LCD_COLOR24
46 #define CONFIG_CMD_BMP
47 #define CONFIG_VIDEO_BMP_RLE8
48 #endif /* CONFIG_LCD */
49 #endif /* CONFIG_SPL_BUILD */
52 * Memory configuration options
54 #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of SDRAM */
55 #define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
56 #define CONFIG_STACKSIZE SZ_64K
57 #define CONFIG_SYS_MALLOC_LEN SZ_4M
58 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
59 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M)
62 * U-Boot general configurations
64 #define CONFIG_SYS_LONGHELP
65 #define CONFIG_SYS_PROMPT "TX28 U-Boot > "
66 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
67 #define CONFIG_SYS_PBSIZE \
68 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
69 /* Print buffer size */
70 #define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
71 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
72 /* Boot argument buffer size */
73 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
74 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
75 #define CONFIG_CMDLINE_EDITING /* Command history etc */
77 #define CONFIG_SYS_64BIT_VSPRINTF
78 #define CONFIG_SYS_NO_FLASH
81 * Flattened Device Tree (FDT) support
83 #define CONFIG_OF_LIBFDT
84 #ifdef CONFIG_OF_LIBFDT
85 #define CONFIG_FDT_FIXUP_PARTITIONS
86 #define CONFIG_OF_BOARD_SETUP
87 #define CONFIG_DEFAULT_DEVICE_TREE tx28
88 #define CONFIG_ARCH_DEVICE_TREE mx28
89 #define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
95 #define xstr(s) str(s)
97 #define __pfx(x, s) (x##s)
98 #define _pfx(x, s) __pfx(x, s)
100 #define CONFIG_CMDLINE_TAG
101 #define CONFIG_SETUP_MEMORY_TAGS
102 #define CONFIG_BOOTDELAY 3
103 #define CONFIG_ZERO_BOOTDELAY_CHECK
104 #define CONFIG_SYS_AUTOLOAD "no"
105 #define CONFIG_BOOTFILE "uImage"
106 #define CONFIG_BOOTARGS "console=ttyAMA0,115200 ro debug panic=1"
107 #define CONFIG_BOOTCOMMAND "run bootcmd_nand"
108 #define CONFIG_LOADADDR 43000000
109 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
110 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
115 #ifdef CONFIG_ENV_IS_NOWHERE
116 #define CONFIG_EXTRA_ENV_SETTINGS \
120 "fdtaddr=11000000\0" \
121 "mtdids=" MTDIDS_DEFAULT "\0" \
122 "mtdparts=" MTDPARTS_DEFAULT "\0"
124 #define CONFIG_EXTRA_ENV_SETTINGS \
126 "baseboard=stk5-v3\0" \
127 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
128 " root=/dev/mmcblk0p3 rootwait\0" \
129 "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
130 " root=/dev/mtdblock3 rootfstype=jffs2\0" \
131 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
132 " root=/dev/nfs ip=dhcp nfsroot=${nfs_server}:${nfsroot},nolock\0" \
133 "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
134 "fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \
135 "bootcmd_nand=set autostart no;run bootargs_nand;" \
136 "nboot linux;run bootm_cmd\0" \
137 "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
139 "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
140 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
141 " ${append_bootargs}\0" \
142 "fdtaddr=41000000\0" \
143 "fdtsave=nand erase.part dtb;nand write ${fdtaddr} dtb ${fdtsize}\0" \
144 "mtdids=" MTDIDS_DEFAULT "\0" \
145 "mtdparts=" MTDPARTS_DEFAULT "\0" \
146 "nfsroot=/tftpboot/rootfs\0" \
147 "otg_mode=device\0" \
148 "touchpanel=tsc2007\0" \
150 #endif /* CONFIG_ENV_IS_NOWHERE */
152 #define MTD_NAME "gpmi-nand"
153 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
158 #include <config_cmd_default.h>
159 #define CONFIG_CMD_CACHE
160 #define CONFIG_CMD_MMC
161 #define CONFIG_CMD_NAND
162 #define CONFIG_CMD_MTDPARTS
163 #define CONFIG_CMD_BOOTCE
164 #define CONFIG_CMD_TIME
165 #define CONFIG_CMD_MEMTEST
170 #define CONFIG_PL011_SERIAL
171 #define CONFIG_PL011_CLOCK 24000000
172 #define CONFIG_PL01x_PORTS { \
173 (void *)MXS_UARTDBG_BASE, \
175 #define CONFIG_CONS_INDEX 0 /* do not change! */
176 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
177 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
178 #define CONFIG_SYS_CONSOLE_INFO_QUIET
183 #define CONFIG_FEC_MXC
184 #ifdef CONFIG_FEC_MXC
185 /* This is required for the FEC driver to work with cache enabled */
186 #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
187 #define CONFIG_SYS_CACHELINE_SIZE 32
189 #ifndef CONFIG_TX28_S
190 #define CONFIG_FEC_MXC_MULTI
192 #define IMX_FEC_BASE MXS_ENET0_BASE
193 #define CONFIG_FEC_MXC_PHYADDR 0x00
196 #define CONFIG_PHY_SMSC
197 #define CONFIG_PHYLIB
199 #define CONFIG_FEC_XCV_TYPE RMII
200 #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
201 #define CONFIG_NET_MULTI
202 #define CONFIG_CMD_MII
203 #define CONFIG_CMD_DHCP
204 #define CONFIG_CMD_PING
205 /* Add for working with "strict" DHCP server */
206 #define CONFIG_BOOTP_SUBNETMASK
207 #define CONFIG_BOOTP_GATEWAY
208 #define CONFIG_BOOTP_DNS
209 #define CONFIG_BOOTP_RANDOM_ID
212 #ifndef CONFIG_ENV_IS_NOWHERE
213 /* define one of the following options:
214 #define CONFIG_ENV_IS_IN_NAND
215 #define CONFIG_ENV_IS_IN_MMC
217 #define CONFIG_ENV_IS_IN_NAND
219 #define CONFIG_ENV_OVERWRITE
224 #ifdef CONFIG_CMD_NAND
225 #define CONFIG_MTD_DEVICE
226 #define CONFIG_NAND_MXS
227 #define CONFIG_APBH_DMA
228 #define CONFIG_APBH_DMA_BURST
229 #define CONFIG_APBH_DMA_BURST8
230 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
231 #define CONFIG_CMD_NAND_TRIMFFS
232 #define CONFIG_SYS_MXS_DMA_CHANNEL 4
233 #define CONFIG_SYS_MAX_FLASH_SECT 1024
234 #define CONFIG_SYS_MAX_FLASH_BANKS 1
235 #define CONFIG_SYS_NAND_MAX_CHIPS 1
236 #define CONFIG_SYS_MAX_NAND_DEVICE 1
237 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
238 #define CONFIG_SYS_NAND_USE_FLASH_BBT
239 #define CONFIG_SYS_NAND_BASE 0x00000000
240 #define CONFIG_CMD_ROMUPDATE
242 #undef CONFIG_ENV_IS_IN_NAND
243 #endif /* CONFIG_CMD_NAND */
245 #define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
246 #define CONFIG_ENV_SIZE SZ_128K
247 #define CONFIG_ENV_RANGE 0x60000
248 #ifdef CONFIG_ENV_OFFSET_REDUND
249 #define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_ENV_RANGE) \
251 xstr(CONFIG_ENV_RANGE) \
253 #define CONFIG_SYS_USERFS_PART_STR "107904k(userfs)"
255 #define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_ENV_RANGE) \
257 #define CONFIG_SYS_USERFS_PART_STR "108288k(userfs)"
258 #endif /* CONFIG_ENV_OFFSET_REDUND */
263 #ifdef CONFIG_CMD_MMC
265 #define CONFIG_GENERIC_MMC
266 #define CONFIG_MXS_MMC
267 #define CONFIG_BOUNCE_BUFFER
269 #define CONFIG_DOS_PARTITION
270 #define CONFIG_CMD_FAT
271 #define CONFIG_CMD_EXT2
274 * Environments on MMC
276 #ifdef CONFIG_ENV_IS_IN_MMC
277 #define CONFIG_SYS_MMC_ENV_DEV 0
278 #undef CONFIG_ENV_OFFSET
279 #undef CONFIG_ENV_SIZE
280 /* Associated with the MMC layout defined in mmcops.c */
281 #define CONFIG_ENV_OFFSET SZ_1K
282 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
283 #define CONFIG_DYNAMIC_MMC_DEVNO
284 #endif /* CONFIG_ENV_IS_IN_MMC */
286 #undef CONFIG_ENV_IS_IN_MMC
287 #endif /* CONFIG_CMD_MMC */
289 #ifdef CONFIG_ENV_IS_NOWHERE
290 #undef CONFIG_ENV_SIZE
291 #define CONFIG_ENV_SIZE SZ_4K
294 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
295 "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \
296 CONFIG_SYS_ENV_PART_STR \
297 "4m(linux),16m(rootfs)," \
298 CONFIG_SYS_USERFS_PART_STR ",256k(dtb),512k@0x7f80000(bbt)ro"
300 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
301 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
302 GENERATED_GBL_DATA_SIZE)
304 /* Defines for SPL */
306 #define CONFIG_SPL_NO_CPU_SUPPORT_CODE
307 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
308 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
309 #define CONFIG_SPL_LIBCOMMON_SUPPORT
310 #define CONFIG_SPL_LIBGENERIC_SUPPORT
311 #define CONFIG_SPL_SERIAL_SUPPORT
312 #define CONFIG_SPL_GPIO_SUPPORT
313 #define CONFIG_SYS_SPL_VDDD_VAL 1500
314 #define CONFIG_SYS_SPL_BATT_BO_LEVEL 2800
315 #define CONFIG_SYS_SPL_VDDMEM_VAL 0 /* VDDMEM is not utilized on TX28 */
317 #endif /* __CONFIGS_TX28_H */