2 * Copyright (C) 2012-2014 <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0
11 #define CONFIG_MX51 /* must be set before including imx-regs.h */
13 #include <asm/sizes.h>
14 #include <asm/arch/imx-regs.h>
17 * Ka-Ro TX51 board - SoC configuration
19 #define CONFIG_SYS_MX5_IOMUX_V3
20 #define CONFIG_MXC_GPIO /* GPIO control */
21 #define CONFIG_SYS_MX5_HCLK 24000000
22 #define CONFIG_SYS_DDR_CLKSEL 0
23 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
24 #define CONFIG_SHOW_ACTIVITY
25 #define CONFIG_DISPLAY_BOARDINFO
26 #define CONFIG_BOARD_LATE_INIT
27 #define CONFIG_BOARD_EARLY_INIT_F
29 #if CONFIG_SYS_CPU_CLK == 600
30 #define TX51_MOD_PREFIX "6"
31 #elif CONFIG_SYS_CPU_CLK == 800
32 #define TX51_MOD_PREFIX "8"
33 #define CONFIG_MX51_PLL_ERRATA
35 #error Invalid CPU clock
38 /* LCD Logo and Splash screen support */
41 #define CONFIG_SPLASH_SCREEN
42 #define CONFIG_SPLASH_SCREEN_ALIGN
43 #define CONFIG_VIDEO_IPUV3
44 #define CONFIG_IPUV3_CLK 133000000
45 #define CONFIG_LCD_LOGO
46 #define LCD_BPP LCD_COLOR24
47 #define CONFIG_CMD_BMP
48 #define CONFIG_VIDEO_BMP_RLE8
49 #endif /* CONFIG_LCD */
52 * Memory configuration options
54 #define PHYS_SDRAM_1 0x90000000 /* Base address of bank 1 */
55 #define PHYS_SDRAM_1_SIZE SZ_128M
56 #if CONFIG_NR_DRAM_BANKS > 1
57 #define PHYS_SDRAM_2 0x98000000 /* Base address of bank 2 */
58 #define PHYS_SDRAM_2_SIZE SZ_128M
60 #define CONFIG_STACKSIZE SZ_128K
61 #define CONFIG_SYS_MALLOC_LEN SZ_8M
62 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
63 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */
64 #define CONFIG_SYS_SDRAM_CLK 166
65 #define CONFIG_SYS_CLKTL_CBCDR 0x01e35100
68 * U-Boot general configurations
70 #define CONFIG_SYS_LONGHELP
71 #define CONFIG_SYS_PROMPT "TX51 U-Boot > "
72 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
73 #define CONFIG_SYS_PBSIZE \
74 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
75 /* Print buffer size */
76 #define CONFIG_SYS_MAXARGS 256 /* Max number of command args */
77 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
78 /* Boot argument buffer size */
79 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
80 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
81 #define CONFIG_CMDLINE_EDITING /* Command history etc */
83 #define CONFIG_SYS_64BIT_VSPRINTF
84 #define CONFIG_SYS_NO_FLASH
87 * Flattened Device Tree (FDT) support
89 #define CONFIG_OF_LIBFDT
90 #define CONFIG_OF_BOARD_SETUP
91 #define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
96 #define xstr(s) str(s)
98 #define __pfx(x, s) (x##s)
99 #define _pfx(x, s) __pfx(x, s)
101 #define CONFIG_CMDLINE_TAG
102 #define CONFIG_SETUP_MEMORY_TAGS
103 #define CONFIG_BOOTDELAY 3
104 #define CONFIG_ZERO_BOOTDELAY_CHECK
105 #define CONFIG_SYS_AUTOLOAD "no"
106 #define CONFIG_BOOTFILE "uImage"
107 #define CONFIG_BOOTARGS "init=/linuxrc console=ttymxc0,115200 ro debug panic=1"
108 #define CONFIG_BOOTCOMMAND "run bootcmd_${boot_mode} bootm_cmd"
109 #define CONFIG_LOADADDR 94000000
110 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
111 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
112 #define CONFIG_HW_WATCHDOG
115 * Extra Environment Settings
117 #define CONFIG_SYS_CPU_CLK_STR xstr(CONFIG_SYS_CPU_CLK)
119 #define CONFIG_EXTRA_ENV_SETTINGS \
121 "baseboard=stk5-v3\0" \
122 "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}" \
123 " root=/dev/mtdblock3 rootfstype=jffs2\0" \
124 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
125 " root=/dev/mmcblk0p2 rootwait\0" \
126 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
127 " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \
129 "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}" \
130 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
131 "bootcmd_jffs2=set autostart no;run bootargs_jffs2" \
133 "bootcmd_mmc=set autostart no;run bootargs_mmc" \
134 ";fatload mmc 0 ${loadaddr} uImage\0" \
135 "bootcmd_nand=set autostart no;run bootargs_ubifs" \
137 "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs" \
139 "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
141 "cpu_clk=" CONFIG_SYS_CPU_CLK_STR "\0" \
142 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
143 " ${append_bootargs}\0" \
144 "fdtaddr=91000000\0" \
145 "fdtsave=fdt resize;nand erase.part dtb" \
146 ";nand write ${fdtaddr} dtb ${fdtsize}\0" \
147 "mtdids=" MTDIDS_DEFAULT "\0" \
148 "mtdparts=" MTDPARTS_DEFAULT "\0" \
149 "nfsroot=/tftpboot/rootfs\0" \
150 "otg_mode=device\0" \
151 "touchpanel=tsc2007\0" \
154 #define MTD_NAME "mxc_nand"
155 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
156 #define CONFIG_FDT_FIXUP_PARTITIONS
161 #include <config_cmd_default.h>
162 #define CONFIG_CMD_CACHE
163 #define CONFIG_CMD_MMC
164 #define CONFIG_CMD_NAND
165 #define CONFIG_CMD_MTDPARTS
166 #define CONFIG_CMD_BOOTCE
167 #define CONFIG_CMD_TIME
168 #define CONFIG_CMD_MEMTEST
173 #define CONFIG_MXC_UART
174 #define CONFIG_MXC_UART_BASE UART1_BASE
175 #define CONFIG_MXC_GPIO
176 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
177 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
178 #define CONFIG_SYS_CONSOLE_INFO_QUIET
183 #define CONFIG_FEC_MXC
184 #ifdef CONFIG_FEC_MXC
185 #define IMX_FEC_BASE FEC_BASE_ADDR
186 #define CONFIG_FEC_MXC_PHYADDR 0x1f
187 #define CONFIG_PHYLIB
188 #define CONFIG_PHY_SMSC
190 #define CONFIG_FEC_XCV_TYPE MII100
191 #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
192 #define CONFIG_CMD_MII
193 #define CONFIG_CMD_DHCP
194 #define CONFIG_CMD_PING
195 /* Add for working with "strict" DHCP server */
196 #define CONFIG_BOOTP_SUBNETMASK
197 #define CONFIG_BOOTP_GATEWAY
198 #define CONFIG_BOOTP_DNS
204 #ifdef CONFIG_CMD_NAND
205 #define CONFIG_MTD_DEVICE
206 #define CONFIG_ENV_IS_IN_NAND
207 #define CONFIG_NAND_MXC
208 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
209 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
210 #define CONFIG_MXC_NAND_HWECC
211 #define CONFIG_CMD_NAND_TRIMFFS
212 #define CONFIG_SYS_NAND_MAX_CHIPS 1
213 #define CONFIG_SYS_MAX_NAND_DEVICE 1
214 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
215 #define CONFIG_SYS_NAND_USE_FLASH_BBT
216 #ifdef CONFIG_ENV_IS_IN_NAND
217 #define CONFIG_ENV_OVERWRITE
218 #define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE
219 #define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
220 #define CONFIG_ENV_RANGE 0x60000
222 #define CONFIG_SYS_NAND_BASE 0x00000000
223 #define CONFIG_CMD_ROMUPDATE
224 #endif /* CONFIG_CMD_NAND */
229 #ifdef CONFIG_CMD_MMC
230 #ifndef CONFIG_ENV_IS_IN_NAND
231 #define CONFIG_ENV_IS_IN_MMC
234 #define CONFIG_GENERIC_MMC
235 #define CONFIG_FSL_ESDHC
236 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
238 #define CONFIG_DOS_PARTITION
239 #define CONFIG_CMD_FAT
240 #define CONFIG_FAT_WRITE
241 #define CONFIG_CMD_EXT2
244 * Environments on MMC
246 #ifdef CONFIG_ENV_IS_IN_MMC
247 #define CONFIG_SYS_MMC_ENV_DEV 0
248 #define CONFIG_ENV_OVERWRITE
249 /* Associated with the MMC layout defined in mmcops.c */
250 #define CONFIG_ENV_OFFSET SZ_1K
251 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
252 #define CONFIG_DYNAMIC_MMC_DEVNO
253 #endif /* CONFIG_ENV_IS_IN_MMC */
254 #endif /* CONFIG_CMD_MMC */
256 #ifdef CONFIG_ENV_OFFSET_REDUND
257 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
259 xstr(CONFIG_ENV_RANGE) \
261 xstr(CONFIG_ENV_RANGE) \
262 "(env2),6m(linux),32m(rootfs),89344k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
264 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
266 xstr(CONFIG_ENV_RANGE) \
267 "(env),6m(linux),32m(rootfs),89728k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
270 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
271 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
272 GENERATED_GBL_DATA_SIZE)
274 #ifdef CONFIG_CMD_IIM
275 #define CONFIG_FSL_IIM
278 #endif /* __CONFIG_H */