2 * Copyright (C) 2012 <LW@KARO-electronics.de>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
17 #include <asm/sizes.h>
20 * Ka-Ro TX53 board - SoC configuration
22 #define CONFIG_TX53 /* TX53 SoM */
23 #define CONFIG_MX53 /* i.MX53 SoC */
24 #define CONFIG_SYS_MX5_IOMUX_V3
25 #define CONFIG_MXC_GPIO /* GPIO control */
26 #define CONFIG_SYS_MX5_HCLK 24000000
27 #define CONFIG_SYS_MX5_CLK32 32768
28 #define CONFIG_SYS_DDR_CLKSEL 0
29 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
30 #define CONFIG_SHOW_ACTIVITY
31 #define CONFIG_DISPLAY_BOARDINFO
32 #define CONFIG_BOARD_LATE_INIT
33 #define CONFIG_BOARD_EARLY_INIT_F
35 /* LCD Logo and Splash screen support */
38 #define CONFIG_SPLASH_SCREEN
39 #define CONFIG_SPLASH_SCREEN_ALIGN
40 #define CONFIG_VIDEO_MX5
41 #define CONFIG_LCD_LOGO
42 #define LCD_BPP LCD_COLOR24
43 #define CONFIG_CMD_BMP
44 #define CONFIG_VIDEO_BMP_RLE8
45 #endif /* CONFIG_LCD */
48 * Memory configurations
50 #define PHYS_SDRAM_1 0x70000000 /* Base address of bank 1 */
51 #define PHYS_SDRAM_1_SIZE SZ_512M
52 #if CONFIG_NR_DRAM_BANKS > 1
53 #define PHYS_SDRAM_2 0xb0000000 /* Base address of bank 2 */
54 #define PHYS_SDRAM_2_SIZE SZ_512M
55 #define TX53_MOD_SUFFIX "1"
57 #define TX53_MOD_SUFFIX "0"
59 #define CONFIG_STACKSIZE SZ_128K
60 #define CONFIG_SYS_MALLOC_LEN SZ_8M
61 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
62 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */
63 #define CONFIG_SYS_SDRAM_CLK 400
66 * U-Boot general configurations
68 #define CONFIG_SYS_LONGHELP
69 #define CONFIG_SYS_PROMPT "TX53 U-Boot > "
70 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
71 #define CONFIG_SYS_PBSIZE \
72 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
73 /* Print buffer size */
74 #define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
75 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
76 /* Boot argument buffer size */
77 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
78 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
79 #define CONFIG_CMDLINE_EDITING /* Command history etc */
81 #define CONFIG_SYS_64BIT_VSPRINTF
82 #define CONFIG_SYS_NO_FLASH
85 * Flattened Device Tree (FDT) support
87 #define CONFIG_OF_LIBFDT
88 #define CONFIG_OF_EMBED
89 #define CONFIG_OF_BOARD_SETUP
90 #define CONFIG_DEFAULT_DEVICE_TREE tx53
91 #define CONFIG_ARCH_DEVICE_TREE mx53
96 #define xstr(s) str(s)
98 #define __pfx(x, s) (x##s)
99 #define _pfx(x, s) __pfx(x, s)
101 #define CONFIG_CMDLINE_TAG
102 #define CONFIG_SETUP_MEMORY_TAGS
103 #define CONFIG_BOOTDELAY 3
104 #define CONFIG_ZERO_BOOTDELAY_CHECK
105 #define CONFIG_SYS_AUTOLOAD "no"
106 #define CONFIG_BOOTFILE "uImage"
107 #define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1"
108 #define CONFIG_BOOTCOMMAND "run bootcmd_nand"
109 #define CONFIG_LOADADDR 78000000
110 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
111 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
112 #define CONFIG_HW_WATCHDOG
117 #define CONFIG_EXTRA_ENV_SETTINGS \
119 "baseboard=stk5-v3\0" \
120 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
121 " root=/dev/mmcblk0p3 rootwait\0" \
122 "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
123 " root=/dev/mtdblock3 rootfstype=jffs2\0" \
124 "nfsroot=/tftpboot/rootfs\0" \
125 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
126 " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
127 "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
128 "mmc read ${loadaddr} 100 3000;run bootm_cmd\0" \
129 "bootcmd_nand=set autostart no;run bootargs_nand;" \
130 "nboot linux;run bootm_cmd\0" \
131 "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
133 "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \
134 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
135 " video=${video_mode} ${append_bootargs}\0" \
137 "fdtaddr=71000000\0" \
138 "mtdids=" MTDIDS_DEFAULT "\0" \
139 "mtdparts=" MTDPARTS_DEFAULT "\0" \
140 "otg_mode=device\0" \
141 "touchpanel=tsc2007\0" \
142 "video_mode=VGA-1:640x480MR-24@60\0"
144 #define MTD_NAME "mxc_nand"
145 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
146 #define CONFIG_FDT_FIXUP_PARTITIONS
151 #include <config_cmd_default.h>
152 #define CONFIG_CMD_CACHE
153 #define CONFIG_CMD_IIM
154 #define CONFIG_CMD_MMC
155 #define CONFIG_CMD_NAND
156 #define CONFIG_CMD_MTDPARTS
157 #define CONFIG_CMD_BOOTCE
158 #define CONFIG_CMD_TIME
163 #define CONFIG_MXC_UART
164 #define CONFIG_MXC_UART_BASE UART1_BASE
165 #define CONFIG_MXC_GPIO
166 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
167 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
168 #define CONFIG_SYS_CONSOLE_INFO_QUIET
173 #define CONFIG_FEC_MXC
174 #ifdef CONFIG_FEC_MXC
175 #define IMX_FEC_BASE FEC_BASE_ADDR
176 #define CONFIG_FEC_MXC_PHYADDR 0
177 #define CONFIG_PHYLIB
178 #define CONFIG_PHY_SMSC
180 #define CONFIG_FEC_XCV_TYPE MII100
181 #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
182 #define CONFIG_CMD_MII
183 #define CONFIG_CMD_DHCP
184 #define CONFIG_CMD_PING
185 /* Add for working with "strict" DHCP server */
186 #define CONFIG_BOOTP_SUBNETMASK
187 #define CONFIG_BOOTP_GATEWAY
188 #define CONFIG_BOOTP_DNS
194 #ifdef CONFIG_CMD_NAND
195 #define CONFIG_MTD_DEVICE
196 #define CONFIG_ENV_IS_IN_NAND
197 #define CONFIG_NAND_MXC
198 #define CONFIG_MXC_NAND_REGS_BASE 0xf7ff0000
199 #define CONFIG_MXC_NAND_IP_BASE 0x63fdb000
200 #define CONFIG_MXC_NAND_HWECC
201 #define CONFIG_CMD_NAND_TRIMFFS
202 #define CONFIG_SYS_MAX_FLASH_SECT 1024
203 #define CONFIG_SYS_MAX_FLASH_BANKS 1
204 #define CONFIG_SYS_NAND_MAX_CHIPS 1
205 #define CONFIG_SYS_MAX_NAND_DEVICE 1
206 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
207 #define CONFIG_SYS_NAND_USE_FLASH_BBT
208 #ifdef CONFIG_ENV_IS_IN_NAND
209 #define CONFIG_ENV_OVERWRITE
210 #define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE
211 #define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
212 #define CONFIG_ENV_RANGE 0x60000
214 #ifndef CONFIG_SYS_NO_FLASH
215 #define CONFIG_CMD_FLASH
216 #define CONFIG_SYS_NAND_BASE 0xa0000000
219 #define CONFIG_SYS_NAND_BASE 0x00000000
220 #define CONFIG_CMD_ROMUPDATE
222 #endif /* CONFIG_CMD_NAND */
227 #ifdef CONFIG_CMD_MMC
228 #ifndef CONFIG_ENV_IS_IN_NAND
229 #define CONFIG_ENV_IS_IN_MMC
232 #define CONFIG_GENERIC_MMC
233 #define CONFIG_FSL_ESDHC
234 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
235 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
236 #define CONFIG_SYS_FSL_ESDHC_NUM 2
238 #define CONFIG_DOS_PARTITION
239 #define CONFIG_CMD_FAT
240 #define CONFIG_CMD_EXT2
243 * Environments on MMC
245 #ifdef CONFIG_ENV_IS_IN_MMC
246 #define CONFIG_SYS_MMC_ENV_DEV 0
247 #define CONFIG_ENV_OVERWRITE
248 /* Associated with the MMC layout defined in mmcops.c */
249 #define CONFIG_ENV_OFFSET SZ_1K
250 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
251 #define CONFIG_DYNAMIC_MMC_DEVNO
252 #endif /* CONFIG_ENV_IS_IN_MMC */
253 #endif /* CONFIG_CMD_MMC */
255 #ifdef CONFIG_ENV_OFFSET_REDUND
256 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
258 xstr(CONFIG_ENV_RANGE) \
260 xstr(CONFIG_ENV_RANGE) \
261 "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
263 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
265 xstr(CONFIG_ENV_RANGE) \
266 "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
269 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
270 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
271 GENERATED_GBL_DATA_SIZE)
273 #ifdef CONFIG_CMD_IIM
274 #define CONFIG_IMX_IIM
277 #endif /* __CONFIG_H */