2 * Copyright (C) 2012 <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0
11 #define CONFIG_MX53 /* must be set before including imx-regs.h */
13 #include <asm/sizes.h>
14 #include <asm/arch/imx-regs.h>
17 * Ka-Ro TX53 board - SoC configuration
19 #define CONFIG_TX53 /* TX53 SoM */
20 #define CONFIG_SYS_MX5_IOMUX_V3
21 #define CONFIG_MXC_GPIO /* GPIO control */
22 #define CONFIG_SYS_MX5_HCLK 24000000
23 #define CONFIG_SYS_DDR_CLKSEL 0
24 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
25 #define CONFIG_SHOW_ACTIVITY
26 #define CONFIG_DISPLAY_BOARDINFO
27 #define CONFIG_BOARD_LATE_INIT
28 #define CONFIG_BOARD_EARLY_INIT_F
30 /* LCD Logo and Splash screen support */
33 #define CONFIG_SPLASH_SCREEN
34 #define CONFIG_SPLASH_SCREEN_ALIGN
35 #define CONFIG_VIDEO_IPUV3
36 #define CONFIG_IPUV3_CLK 200000000
37 #define CONFIG_LCD_LOGO
38 #define LCD_BPP LCD_COLOR24
39 #define CONFIG_CMD_BMP
40 #define CONFIG_VIDEO_BMP_RLE8
41 #endif /* CONFIG_LCD */
43 #ifdef CONFIG_SYS_LVDS_IF
50 * Memory configurations
52 #define PHYS_SDRAM_1 0x70000000 /* Base address of bank 1 */
53 #define PHYS_SDRAM_1_SIZE SZ_512M
54 #if CONFIG_NR_DRAM_BANKS > 1
55 #define PHYS_SDRAM_2 0xb0000000 /* Base address of bank 2 */
56 #define PHYS_SDRAM_2_SIZE SZ_512M
57 #define TX53_MOD_SUFFIX "1"
59 #define TX53_MOD_SUFFIX "0"
61 #define CONFIG_STACKSIZE SZ_128K
62 #define CONFIG_SYS_MALLOC_LEN SZ_8M
63 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
64 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */
65 #define CONFIG_SYS_SDRAM_CLK 400
68 * U-Boot general configurations
70 #define CONFIG_SYS_LONGHELP
71 #define CONFIG_SYS_PROMPT "TX53 U-Boot > "
72 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
73 #define CONFIG_SYS_PBSIZE \
74 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
75 /* Print buffer size */
76 #define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
77 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
78 /* Boot argument buffer size */
79 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
80 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
81 #define CONFIG_CMDLINE_EDITING /* Command history etc */
83 #define CONFIG_SYS_64BIT_VSPRINTF
84 #define CONFIG_SYS_NO_FLASH
87 * Flattened Device Tree (FDT) support
89 #define CONFIG_OF_LIBFDT
90 #define CONFIG_OF_BOARD_SETUP
91 #define CONFIG_DEFAULT_DEVICE_TREE tx53
92 #define CONFIG_ARCH_DEVICE_TREE mx53
93 #define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
98 #define xstr(s) str(s)
100 #define __pfx(x, s) (x##s)
101 #define _pfx(x, s) __pfx(x, s)
103 #define CONFIG_CMDLINE_TAG
104 #define CONFIG_SETUP_MEMORY_TAGS
105 #define CONFIG_BOOTDELAY 3
106 #define CONFIG_ZERO_BOOTDELAY_CHECK
107 #define CONFIG_SYS_AUTOLOAD "no"
108 #define CONFIG_BOOTFILE "uImage"
109 #define CONFIG_BOOTARGS "init=/linuxrc console=ttymxc0,115200 ro debug panic=1"
110 #define CONFIG_BOOTCOMMAND "run bootcmd_${boot_mode} bootm_cmd"
111 #define CONFIG_LOADADDR 78000000
112 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
113 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
114 #define CONFIG_HW_WATCHDOG
119 #define CONFIG_EXTRA_ENV_SETTINGS \
121 "baseboard=stk5-v3\0" \
122 "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}" \
123 " root=/dev/mtdblock3 rootfstype=jffs2\0" \
124 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
125 " root=/dev/mmcblk0p2 rootwait\0" \
126 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
127 " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \
129 "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}" \
130 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
131 "bootcmd_jffs2=set autostart no;run bootargs_jffs2" \
133 "bootcmd_mmc=set autostart no;run bootargs_mmc" \
134 ";fatload mmc 0 ${loadaddr} uImage\0" \
135 "bootcmd_nand=set autostart no;run bootargs_ubifs" \
137 "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs" \
139 "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
142 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
143 " ${append_bootargs}\0" \
144 "fdtaddr=71000000\0" \
145 "fdtsave=nand erase.part dtb" \
146 ";nand write ${fdtaddr} dtb ${fdtsize}\0" \
147 "mtdids=" MTDIDS_DEFAULT "\0" \
148 "mtdparts=" MTDPARTS_DEFAULT "\0" \
149 "nfsroot=/tftpboot/rootfs\0" \
150 "otg_mode=device\0" \
151 "touchpanel=tsc2007\0" \
154 #define MTD_NAME "mxc_nand"
155 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
156 #define CONFIG_FDT_FIXUP_PARTITIONS
161 #include <config_cmd_default.h>
162 #define CONFIG_CMD_CACHE
163 #define CONFIG_CMD_MMC
164 #define CONFIG_CMD_NAND
165 #define CONFIG_CMD_MTDPARTS
166 #define CONFIG_CMD_BOOTCE
167 #define CONFIG_CMD_TIME
168 #define CONFIG_CMD_I2C
169 #define CONFIG_CMD_MEMTEST
174 #define CONFIG_MXC_UART
175 #define CONFIG_MXC_UART_BASE UART1_BASE
176 #define CONFIG_MXC_GPIO
177 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
178 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
179 #define CONFIG_SYS_CONSOLE_INFO_QUIET
184 #define CONFIG_FEC_MXC
185 #ifdef CONFIG_FEC_MXC
186 #define IMX_FEC_BASE FEC_BASE_ADDR
187 #define CONFIG_FEC_MXC_PHYADDR 0
188 #define CONFIG_PHYLIB
189 #define CONFIG_PHY_SMSC
191 #define CONFIG_FEC_XCV_TYPE MII100
192 #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
193 #define CONFIG_CMD_MII
194 #define CONFIG_CMD_DHCP
195 #define CONFIG_CMD_PING
196 /* Add for working with "strict" DHCP server */
197 #define CONFIG_BOOTP_SUBNETMASK
198 #define CONFIG_BOOTP_GATEWAY
199 #define CONFIG_BOOTP_DNS
205 #ifdef CONFIG_CMD_I2C
206 #define CONFIG_HARD_I2C
207 #define CONFIG_I2C_MXC
208 #define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
209 #define CONFIG_SYS_I2C_MX6_PORT1
210 #define CONFIG_SYS_I2C_SPEED 400000
211 #define CONFIG_SYS_I2C_SLAVE 0x34
217 #ifdef CONFIG_CMD_NAND
218 #define CONFIG_MTD_DEVICE
219 #define CONFIG_ENV_IS_IN_NAND
220 #define CONFIG_NAND_MXC
221 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
222 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
223 #define CONFIG_MXC_NAND_HWECC
224 #define CONFIG_CMD_NAND_TRIMFFS
225 #define CONFIG_SYS_MAX_FLASH_SECT 1024
226 #define CONFIG_SYS_MAX_FLASH_BANKS 1
227 #define CONFIG_SYS_NAND_MAX_CHIPS 1
228 #define CONFIG_SYS_MAX_NAND_DEVICE 1
229 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
230 #define CONFIG_SYS_NAND_USE_FLASH_BBT
231 #ifdef CONFIG_ENV_IS_IN_NAND
232 #define CONFIG_ENV_OVERWRITE
233 #define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE
234 #define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
235 #define CONFIG_ENV_RANGE 0x60000
237 #ifndef CONFIG_SYS_NO_FLASH
238 #define CONFIG_CMD_FLASH
239 #define CONFIG_SYS_NAND_BASE 0xa0000000
242 #define CONFIG_SYS_NAND_BASE 0x00000000
243 #define CONFIG_CMD_ROMUPDATE
245 #endif /* CONFIG_CMD_NAND */
250 #ifdef CONFIG_CMD_MMC
251 #ifndef CONFIG_ENV_IS_IN_NAND
252 #define CONFIG_ENV_IS_IN_MMC
255 #define CONFIG_GENERIC_MMC
256 #define CONFIG_FSL_ESDHC
257 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
258 #define CONFIG_SYS_FSL_ESDHC_NUM 2
260 #define CONFIG_DOS_PARTITION
261 #define CONFIG_CMD_FAT
262 #define CONFIG_CMD_EXT2
265 * Environments on MMC
267 #ifdef CONFIG_ENV_IS_IN_MMC
268 #define CONFIG_SYS_MMC_ENV_DEV 0
269 #define CONFIG_ENV_OVERWRITE
270 /* Associated with the MMC layout defined in mmcops.c */
271 #define CONFIG_ENV_OFFSET SZ_1K
272 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
273 #define CONFIG_DYNAMIC_MMC_DEVNO
274 #endif /* CONFIG_ENV_IS_IN_MMC */
275 #endif /* CONFIG_CMD_MMC */
277 #ifdef CONFIG_ENV_OFFSET_REDUND
278 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
280 xstr(CONFIG_ENV_RANGE) \
282 xstr(CONFIG_ENV_RANGE) \
283 "(env2),4m(linux),16m(rootfs),108032k(userfs),256k(dtb),512k@0x7f80000(bbt)ro"
285 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
287 xstr(CONFIG_ENV_RANGE) \
288 "(env),4m(linux),16m(rootfs),108416k(userfs),256k(dtb),512k@0x7f80000(bbt)ro"
291 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
292 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
293 GENERATED_GBL_DATA_SIZE)
295 #ifdef CONFIG_CMD_IIM
296 #define CONFIG_FSL_IIM
299 #endif /* __CONFIG_H */