9 #define CLKID_HDMI_PLL 2
10 #define CLKID_FCLK_DIV2 4
11 #define CLKID_FCLK_DIV3 5
12 #define CLKID_FCLK_DIV4 6
13 #define CLKID_GP0_PLL 9
14 #define CLKID_CLK81 12
15 #define CLKID_MPLL2 15
17 #define CLKID_SAR_ADC 23
21 #define CLKID_AIU_GLUE 38
22 #define CLKID_I2S_OUT 40
23 #define CLKID_MIXER_IFACE 44
28 #define CLKID_HDMI_PCLK 63
29 #define CLKID_USB1_DDR_BRIDGE 64
30 #define CLKID_USB0_DDR_BRIDGE 65
32 #define CLKID_GCLK_VENCI_INT0 77
33 #define CLKID_AOCLK_GATE 80
34 #define CLKID_AO_I2C 93
35 #define CLKID_SD_EMMC_A 94
36 #define CLKID_SD_EMMC_B 95
37 #define CLKID_SD_EMMC_C 96
38 #define CLKID_SAR_ADC_CLK 97
39 #define CLKID_SAR_ADC_SEL 98
40 #define CLKID_MALI_0_SEL 100
41 #define CLKID_MALI_0 102
42 #define CLKID_MALI_1_SEL 103
43 #define CLKID_MALI_1 105
44 #define CLKID_MALI 106
46 #endif /* __GXBB_CLKC_H */