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1 /*
2  * (C) Copyright 2009 Faraday Technology
3  * Po-Yu Chuang <ratbert@faraday-tech.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 /*
9  * SDRAM Controller
10  */
11 #ifndef __FTSDMC020_H
12 #define __FTSDMC020_H
13
14 #define FTSDMC020_OFFSET_TP0            0x00
15 #define FTSDMC020_OFFSET_TP1            0x04
16 #define FTSDMC020_OFFSET_CR             0x08
17 #define FTSDMC020_OFFSET_BANK0_BSR      0x0C
18 #define FTSDMC020_OFFSET_BANK1_BSR      0x10
19 #define FTSDMC020_OFFSET_BANK2_BSR      0x14
20 #define FTSDMC020_OFFSET_BANK3_BSR      0x18
21 #define FTSDMC020_OFFSET_BANK4_BSR      0x1C
22 #define FTSDMC020_OFFSET_BANK5_BSR      0x20
23 #define FTSDMC020_OFFSET_BANK6_BSR      0x24
24 #define FTSDMC020_OFFSET_BANK7_BSR      0x28
25 #define FTSDMC020_OFFSET_ACR            0x34
26
27 /*
28  * Timing Parametet 0 Register
29  */
30 #define FTSDMC020_TP0_TCL(x)    ((x) & 0x3)
31 #define FTSDMC020_TP0_TWR(x)    (((x) & 0x3) << 4)
32 #define FTSDMC020_TP0_TRF(x)    (((x) & 0xf) << 8)
33 #define FTSDMC020_TP0_TRCD(x)   (((x) & 0x7) << 12)
34 #define FTSDMC020_TP0_TRP(x)    (((x) & 0xf) << 16)
35 #define FTSDMC020_TP0_TRAS(x)   (((x) & 0xf) << 20)
36
37 /*
38  * Timing Parametet 1 Register
39  */
40 #define FTSDMC020_TP1_REF_INTV(x)       ((x) & 0xffff)
41 #define FTSDMC020_TP1_INI_REFT(x)       (((x) & 0xf) << 16)
42 #define FTSDMC020_TP1_INI_PREC(x)       (((x) & 0xf) << 20)
43
44 /*
45  * Configuration Register
46  */
47 #define FTSDMC020_CR_SREF       (1 << 0)
48 #define FTSDMC020_CR_PWDN       (1 << 1)
49 #define FTSDMC020_CR_ISMR       (1 << 2)
50 #define FTSDMC020_CR_IREF       (1 << 3)
51 #define FTSDMC020_CR_IPREC      (1 << 4)
52 #define FTSDMC020_CR_REFTYPE    (1 << 5)
53
54 /*
55  * SDRAM External Bank Base/Size Register
56  */
57 #define FTSDMC020_BANK_ENABLE           (1 << 28)
58
59 #define FTSDMC020_BANK_BASE(addr)       (((addr) >> 20) << 16)
60
61 #define FTSDMC020_BANK_DDW_X4           (0 << 12)
62 #define FTSDMC020_BANK_DDW_X8           (1 << 12)
63 #define FTSDMC020_BANK_DDW_X16          (2 << 12)
64 #define FTSDMC020_BANK_DDW_X32          (3 << 12)
65
66 #define FTSDMC020_BANK_DSZ_16M          (0 << 8)
67 #define FTSDMC020_BANK_DSZ_64M          (1 << 8)
68 #define FTSDMC020_BANK_DSZ_128M         (2 << 8)
69 #define FTSDMC020_BANK_DSZ_256M         (3 << 8)
70
71 #define FTSDMC020_BANK_MBW_8            (0 << 4)
72 #define FTSDMC020_BANK_MBW_16           (1 << 4)
73 #define FTSDMC020_BANK_MBW_32           (2 << 4)
74
75 #define FTSDMC020_BANK_SIZE_1M          0x0
76 #define FTSDMC020_BANK_SIZE_2M          0x1
77 #define FTSDMC020_BANK_SIZE_4M          0x2
78 #define FTSDMC020_BANK_SIZE_8M          0x3
79 #define FTSDMC020_BANK_SIZE_16M         0x4
80 #define FTSDMC020_BANK_SIZE_32M         0x5
81 #define FTSDMC020_BANK_SIZE_64M         0x6
82 #define FTSDMC020_BANK_SIZE_128M        0x7
83 #define FTSDMC020_BANK_SIZE_256M        0x8
84
85 /*
86  * Arbiter Control Register
87  */
88 #define FTSDMC020_ACR_TOC(x)    ((x) & 0x1f)
89 #define FTSDMC020_ACR_TOE       (1 << 8)
90
91 #endif  /* __FTSDMC020_H */