2 * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #define IMX_SPI_ACTIVE_HIGH 1
31 #define IMX_SPI_ACTIVE_LOW 0
32 #define SPI_RETRY_TIMES 100
34 #if defined(IMX_CSPI_VER_0_7)
35 #define SPI_RX_DATA 0x0
36 #define SPI_TX_DATA 0x4
37 #define SPI_CON_REG 0x8
38 #define SPI_INT_REG 0xC
39 #define SPI_DMA_REG 0x10
40 #define SPI_STAT_REG 0x14
41 #define SPI_PERIOD_REG 0x18
43 #define SPI_CTRL_EN (1 << 0)
44 #define SPI_CTRL_MODE (1 << 1)
45 #define SPI_CTRL_REG_XCH_BIT (1 << 2)
46 #define SPI_CTRL_SSPOL (1 << 7)
47 #define SPI_CTRL_SSPOL_OFF (7)
48 #define SPI_CTRL_SSCTL (1 << 6)
49 #define SPI_CTRL_SSCTL_OFF (6)
50 #define SPI_CTRL_SCLK_POL (1 << 4)
51 #define SPI_CTRL_SCLK_POL_OFF (4)
52 #define SPI_CTRL_SCLK_PHA (1 << 5)
53 #define SPI_CTRL_SCLK_PHA_OFF (5)
54 #define SPI_CTRL_SS_OFF (12)
55 #define SPI_CTRL_SS_MASK (3 << 12)
56 #define SPI_CTRL_DATA_OFF (16)
57 #define SPI_CTRL_DATA_MASK (7 << 16)
58 #define SPI_CTRL_BURST_OFF (20)
59 #define SPI_CTRL_BURST_MASK (0xFFF << 20)
60 #define SPI_INT_STAT_TC (1 << 7)
62 #elif defined(IMX_CSPI_VER_2_3)
63 #define SPI_RX_DATA 0x0
64 #define SPI_TX_DATA 0x4
65 #define SPI_CON_REG 0x8
66 #define SPI_CFG_REG 0xC
67 #define SPI_INT_REG 0x10
68 #define SPI_DMA_REG 0x14
69 #define SPI_STAT_REG 0x18
70 #define SPI_PERIOD_REG 0x1C
78 struct imx_spi_dev_t {
79 struct spi_slave slave;
80 u32 base; /* base address of SPI module the device is connected to */
81 u32 freq; /* desired clock freq in Hz for this device */
82 u32 ss_pol; /* ss polarity: 1=active high; 0=active low */
83 u32 ss; /* slave select */
84 u32 in_sctl; /* inactive sclk ctl: 1=stay low; 0=stay high */
85 u32 in_dctl; /* inactive data ctl: 1=stay low; 0=stay high */
86 u32 ssctl; /* single burst mode vs multiple: 0=single; 1=multi */
87 u32 sclkpol; /* sclk polarity: active high=0; active low=1 */
88 u32 sclkpha; /* sclk phase: 0=phase 0; 1=phase1 */
89 u32 fifo_sz; /* fifo size in bytes for either tx or rx. Don't add them up! */
90 u32 us_delay; /* us delay in each xfer */
91 struct spi_reg_t reg; /* pointer to a set of SPI registers */
94 extern void spi_io_init(struct imx_spi_dev_t *dev);
96 #endif /* __IMX_SPI_H__ */