2 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #ifndef _IMX_SPI_NOR_H_
24 #define _IMX_SPI_NOR_H_
26 #define READ 0x03 /* tx:1 byte cmd + 3 byte addr;rx:variable bytes */
27 #define READ_HS 0x0B /* tx:1 byte cmd + 3 byte addr + 1 byte dummy; */
28 #define RDSR 0x05 /* read stat reg 1 byte tx cmd + 1 byte rx status */
29 #define RDSR_BUSY (1 << 0) /* 1=write-in-progress (default 0) */
30 #define RDSR_WEL (1 << 1) /* 1=write enable (default 0) */
31 #define RDSR_BP0 (1 << 2) /* block write prot level (default 1) */
32 #define RDSR_BP1 (1 << 3) /* block write prot level (default 1) */
33 #define RDSR_BP2 (1 << 4) /* block write prot level (default 1) */
34 #define RDSR_BP3 (1 << 5) /* block write prot level (default 1) */
35 #define RDSR_AAI (1 << 6) /* 1=AAI prog mode; 0=byte prog (def 0) */
36 #define RDSR_BPL (1 << 7) /* 1=BP3,BP2,BP1,BP0 RO; 0=R/W (def 0) */
37 #define WREN 0x06 /* write enable. 1 byte tx cmd */
38 #define WRDI 0x04 /* write disable. 1 byte tx cmd */
39 #define EWSR 0x50 /* Enable write status. 1 byte tx cmd */
40 #define WRSR 0x01 /* Write stat reg. 1 byte tx cmd + 1 byte tx val */
41 #define ERASE_4K 0x20 /* sector erase. 1 byte cmd + 3 byte addr */
42 #define ERASE_32K 0x52 /* 32K block erase. 1 byte cmd + 3 byte addr */
43 #define ERASE_64K 0xD8 /* 64K block erase. 1 byte cmd + 3 byte addr */
44 #define ERASE_CHIP 0x60 /* whole chip erase */
45 #define BYTE_PROG 0x02 /* all tx: 1 cmd + 3 addr + 1 data */
46 #define AAI_PROG 0xAD /* all tx: [1 cmd + 3 addr + 2 data] + RDSR */
47 /* + [1cmd + 2 data] + .. + [WRDI] + [RDSR] */
48 #define JEDEC_ID 0x9F /* read JEDEC ID. tx: 1 byte cmd; rx: 3 byte ID */
50 /* Atmel SPI-NOR commands */
51 #define WR_2_MEM_DIR 0x82
54 #define BUF1_TO_MEM 0x83
55 #define BUF2_TO_MEM 0x86
56 #define STAT_READ 0xD7
57 #define STAT_PG_SZ (1 << 0) /* 1=Page size is 512, 0=Page size is 528 */
58 #define STAT_PROT (1 << 1) /* 1=sector protection enabled (default 0) */
59 #define STAT_COMP (1 << 6)
60 #define STAT_BUSY (1 << 7) /* 1=Device not busy */
61 #define CONFIG_REG1 0x3D
62 #define CONFIG_REG2 0x2A
63 #define CONFIG_REG3 0x80
64 #define CONFIG_REG4 0xA6
66 #define SZ_64K 0x10000
70 #endif /* _IMX_SPI_NOR_H_ */