5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
9 * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #ifndef __ASM_ARCH_IPU_H__
31 #define __ASM_ARCH_IPU_H__
33 #include <linux/types.h>
34 #include <linux/list.h>
39 #define IDMA_CHAN_INVALID 0xFF
40 #define HIGH_RESOLUTION_WIDTH 1024
43 * Enumeration of Synchronous (Memory-less) panel types
50 /* IPU Pixel format definitions */
51 #define fourcc(a, b, c, d)\
52 (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
55 * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
56 * the same used by V4L2 API.
59 #define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0')
60 #define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1')
61 #define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6')
62 #define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8')
64 #define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*< 8 RGB-3-3-2 */
65 #define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*< 16 RGB-5-5-5 */
66 #define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */
67 #define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */
68 #define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */
69 #define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*< 24 BGR-8-8-8 */
70 #define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*< 24 RGB-8-8-8 */
71 #define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*< 32 BGR-8-8-8-8 */
72 #define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*< 32 BGR-8-8-8-8 */
73 #define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*< 32 RGB-8-8-8-8 */
74 #define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*< 32 RGB-8-8-8-8 */
75 #define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*< 32 ABGR-8-8-8-8 */
77 /* YUV Interleaved Formats */
78 #define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*< 16 YUV 4:2:2 */
79 #define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*< 16 YUV 4:2:2 */
80 #define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*< 12 YUV 4:1:1 */
81 #define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*< 24 YUV 4:4:4 */
83 /* two planes -- one Y, one Cb + Cr interleaved */
84 #define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
86 #define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*< 8 Greyscale */
87 #define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*< 9 YVU 4:1:0 */
88 #define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*< 9 YUV 4:1:0 */
89 #define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*< 12 YVU 4:2:0 */
90 #define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*< 12 YUV 4:2:0 */
91 #define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*< 12 YUV 4:2:0 */
92 #define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */
93 #define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */
96 * IPU Driver channels definitions.
97 * Note these are different from IDMA channels
100 #define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
101 ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
102 #define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))
103 #define IPU_CHAN_ID(ch) (ch >> 24)
104 #define IPU_CHAN_ALT(ch) (ch & 0x02000000)
105 #define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F)
106 #define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F)
107 #define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F)
108 #define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F))
113 * Enumeration of IPU logical channels. An IPU logical channel is defined as a
114 * combination of an input (memory to IPU), output (IPU to memory), and/or
115 * secondary input IDMA channels and in some cases an Image Converter task.
116 * Some channels consist of only an input or output.
121 MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
122 MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
123 MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
124 MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
126 MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
127 MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
128 MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
129 MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
131 DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
132 DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
137 * Enumeration of types of buffers for a logical channel.
140 IPU_OUTPUT_BUFFER = 0, /* Buffer for output from IPU */
141 IPU_ALPHA_IN_BUFFER = 1, /* Buffer for input to IPU */
142 IPU_GRAPH_IN_BUFFER = 2, /* Buffer for input to IPU */
143 IPU_VIDEO_IN_BUFFER = 3, /* Buffer for input to IPU */
144 IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
145 IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
150 * Enumeration of version of IPU V3 .
153 IPUV3_HW_REV_IPUV3DEX = 2, /* IPUv3D, IPUv3E IPUv3EX */
154 IPUV3_HW_REV_IPUV3M = 3, /* IPUv3M */
155 IPUV3_HW_REV_IPUV3H = 4, /* IPUv3H */
159 #define IPU_PANEL_SERIAL 1
160 #define IPU_PANEL_PARALLEL 2
171 DMFC_HIGH_RESOLUTION_DC,
172 DMFC_HIGH_RESOLUTION_DP,
173 DMFC_HIGH_RESOLUTION_ONLY_DP,
178 * Union of initialization parameters for a logical channel.
183 unsigned char interlaced;
190 unsigned char interlaced;
191 uint32_t in_pixel_fmt;
192 uint32_t out_pixel_fmt;
193 unsigned char alpha_chan_en;
200 unsigned char interlaced;
201 uint32_t in_pixel_fmt;
202 uint32_t out_pixel_fmt;
203 unsigned char alpha_chan_en;
205 } ipu_channel_params_t;
208 * Bitfield of Display Interface signal polarities.
211 unsigned datamask_en:1;
213 unsigned interlaced:1;
214 unsigned odd_field_first:1;
215 unsigned clksel_en:1;
216 unsigned clkidle_en:1;
217 unsigned data_pol:1; /* true = inverted */
218 unsigned clk_pol:1; /* true = rising edge */
219 unsigned enable_pol:1;
220 unsigned Hsync_pol:1; /* true = active high */
221 unsigned Vsync_pol:1;
222 } ipu_di_signal_cfg_t;
234 } ipu_di_clk_parent_t;
237 int ipuv3_fb_init(struct fb_videomode *mode, int di,
238 unsigned int interface_pix_fmt,
239 ipu_di_clk_parent_t di_clk_parent,
240 unsigned long di_clk_val, int bpp);
242 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);
243 void ipu_uninit_channel(ipu_channel_t channel);
245 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
247 uint16_t width, uint16_t height,
249 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
250 uint32_t u_offset, uint32_t v_offset);
252 int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
253 uint32_t bufNum, dma_addr_t phyaddr);
255 int32_t ipu_is_channel_busy(ipu_channel_t channel);
256 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
258 int32_t ipu_enable_channel(ipu_channel_t channel);
259 int32_t ipu_disable_channel(ipu_channel_t channel);
261 int32_t ipu_init_sync_panel(int disp,
263 uint16_t width, uint16_t height,
265 uint16_t h_start_width, uint16_t h_sync_width,
266 uint16_t h_end_width, uint16_t v_start_width,
267 uint16_t v_sync_width, uint16_t v_end_width,
268 uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
270 int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
272 int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
275 uint32_t bytes_per_pixel(uint32_t fmt);
277 int clk_enable(struct clk *clk);
278 void clk_disable(struct clk *clk);
279 u32 clk_get_rate(struct clk *clk);
280 int clk_set_rate(struct clk *clk, unsigned long rate);
281 long clk_round_rate(struct clk *clk, unsigned long rate);
282 int clk_set_parent(struct clk *clk, struct clk *parent);
283 int clk_get_usecount(struct clk *clk);
284 struct clk *clk_get_parent(struct clk *clk);
286 void ipu_dump_registers(void);
287 int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val);
289 void ipu_dmfc_init(int dmfc_type, int first);
290 void ipu_init_dc_mappings(void);
291 void ipu_dmfc_set_wait4eot(int dma_chan, int width);
292 void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);
293 void ipu_dc_uninit(int dc_chan);
294 void ipu_dp_dc_enable(ipu_channel_t channel);
295 int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
296 uint32_t out_pixel_fmt);
297 void ipu_dp_uninit(ipu_channel_t channel);
298 void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);
299 ipu_color_space_t format_to_colorspace(uint32_t fmt);