2 * Copyright (C) 2015, 2016 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __KVM_ARM_VGIC_H
17 #define __KVM_ARM_VGIC_H
19 #include <linux/kernel.h>
20 #include <linux/kvm.h>
21 #include <linux/irqreturn.h>
22 #include <linux/spinlock.h>
23 #include <linux/static_key.h>
24 #include <linux/types.h>
25 #include <kvm/iodev.h>
26 #include <linux/list.h>
27 #include <linux/jump_label.h>
29 #define VGIC_V3_MAX_CPUS 255
30 #define VGIC_V2_MAX_CPUS 8
31 #define VGIC_NR_IRQS_LEGACY 256
32 #define VGIC_NR_SGIS 16
33 #define VGIC_NR_PPIS 16
34 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
35 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
36 #define VGIC_MAX_SPI 1019
37 #define VGIC_MAX_RESERVED 1023
38 #define VGIC_MIN_LPI 8192
39 #define KVM_IRQCHIP_NUM_PINS (1020 - 32)
41 #define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
44 VGIC_V2, /* Good ol' GICv2 */
45 VGIC_V3, /* New fancy GICv3 */
48 /* same for all guests, as depending only on the _host's_ GIC model */
50 /* type of the host GIC */
53 /* Physical address of vgic virtual cpu interface */
54 phys_addr_t vcpu_base;
57 void __iomem *vcpu_base_va;
59 /* virtual control interface mapping */
60 void __iomem *vctrl_base;
62 /* Number of implemented list registers */
65 /* Maintenance IRQ number */
66 unsigned int maint_irq;
68 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
71 /* Only needed for the legacy KVM_CREATE_IRQCHIP */
72 bool can_emulate_gicv2;
74 /* GIC system register CPU interface */
75 struct static_key_false gicv3_cpuif;
80 extern struct vgic_global kvm_vgic_global_state;
82 #define VGIC_V2_MAX_LRS (1 << 6)
83 #define VGIC_V3_MAX_LRS 16
84 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
86 enum vgic_irq_config {
92 spinlock_t irq_lock; /* Protects the content of the struct */
93 struct list_head lpi_list; /* Used to link all LPIs together */
94 struct list_head ap_list;
96 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
97 * SPIs and LPIs: The VCPU whose ap_list
101 struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should
102 * be sent to, as a result of the
103 * targets reg (v2) or the
107 u32 intid; /* Guest visible INTID */
108 bool line_level; /* Level only */
109 bool pending_latch; /* The pending latch state used to calculate
110 * the pending state for both level
111 * and edge triggered IRQs. */
112 bool active; /* not used for LPIs */
114 bool hw; /* Tied to HW IRQ */
115 struct kref refcount; /* Used for LPIs */
116 u32 hwintid; /* HW INTID number */
118 u8 targets; /* GICv2 target VCPUs mask */
119 u32 mpidr; /* GICv3 target VCPU */
121 u8 source; /* GICv2 SGIs only */
123 enum vgic_irq_config config; /* Level or edge */
125 void *owner; /* Opaque pointer to reserve an interrupt
126 for in-kernel devices. */
129 struct vgic_register_region;
139 struct vgic_io_device {
142 struct kvm_vcpu *redist_vcpu;
143 struct vgic_its *its;
145 const struct vgic_register_region *regions;
146 enum iodev_type iodev_type;
148 struct kvm_io_device dev;
152 /* The base address of the ITS control register frame */
156 struct vgic_io_device iodev;
157 struct kvm_device *dev;
159 /* These registers correspond to GITS_BASER{0,1} */
160 u64 baser_device_table;
161 u64 baser_coll_table;
163 /* Protects the command queue */
164 struct mutex cmd_lock;
169 /* migration ABI revision in use */
172 /* Protects the device and collection lists */
173 struct mutex its_lock;
174 struct list_head device_list;
175 struct list_head collection_list;
178 struct vgic_state_iter;
185 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
188 /* Do injected MSIs require an additional device ID? */
189 bool msis_require_devid;
193 /* TODO: Consider moving to global state */
194 /* Virtual control interface mapping */
195 void __iomem *vctrl_base;
197 /* base addresses in guest physical address space: */
198 gpa_t vgic_dist_base; /* distributor */
200 /* either a GICv2 CPU interface */
202 /* or a number of GICv3 redistributor regions */
203 gpa_t vgic_redist_base;
206 /* distributor enabled */
209 struct vgic_irq *spis;
211 struct vgic_io_device dist_iodev;
216 * Contains the attributes and gpa of the LPI configuration table.
217 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
218 * one address across all redistributors.
219 * GICv3 spec: 6.1.2 "LPI Configuration tables"
223 /* Protects the lpi_list and the count value below. */
224 spinlock_t lpi_list_lock;
225 struct list_head lpi_list_head;
228 /* used by vgic-debug */
229 struct vgic_state_iter *iter;
232 struct vgic_v2_cpu_if {
235 u64 vgic_elrsr; /* Saved only */
237 u32 vgic_lr[VGIC_V2_MAX_LRS];
240 struct vgic_v3_cpu_if {
243 u32 vgic_sre; /* Restored only, change ignored */
244 u32 vgic_elrsr; /* Saved only */
247 u64 vgic_lr[VGIC_V3_MAX_LRS];
251 /* CPU vif control registers for world switch */
253 struct vgic_v2_cpu_if vgic_v2;
254 struct vgic_v3_cpu_if vgic_v3;
257 unsigned int used_lrs;
258 struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
260 spinlock_t ap_list_lock; /* Protects the ap_list */
263 * List of IRQs that this VCPU should consider because they are either
264 * Active or Pending (hence the name; AP list), or because they recently
265 * were one of the two and need to be migrated off this list to another
268 struct list_head ap_list_head;
271 * Members below are used with GICv3 emulation only and represent
272 * parts of the redistributor.
274 struct vgic_io_device rd_iodev;
275 struct vgic_io_device sgi_iodev;
277 /* Contains the attributes and gpa of the LPI pending tables. */
282 /* Cache guest priority bits */
285 /* Cache guest interrupt ID bits */
289 extern struct static_key_false vgic_v2_cpuif_trap;
291 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
292 void kvm_vgic_early_init(struct kvm *kvm);
293 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
294 int kvm_vgic_create(struct kvm *kvm, u32 type);
295 void kvm_vgic_destroy(struct kvm *kvm);
296 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
297 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
298 int kvm_vgic_map_resources(struct kvm *kvm);
299 int kvm_vgic_hyp_init(void);
300 void kvm_vgic_init_cpu_hardware(void);
302 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
303 bool level, void *owner);
304 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
305 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
306 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
308 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
310 void kvm_vgic_load(struct kvm_vcpu *vcpu);
311 void kvm_vgic_put(struct kvm_vcpu *vcpu);
313 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
314 #define vgic_initialized(k) ((k)->arch.vgic.initialized)
315 #define vgic_ready(k) ((k)->arch.vgic.ready)
316 #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
317 ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
319 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
320 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
321 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
323 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
326 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
328 * The host's GIC naturally limits the maximum amount of VCPUs a guest
331 static inline int kvm_vgic_get_max_vcpus(void)
333 return kvm_vgic_global_state.max_gic_vcpus;
336 int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);
339 * kvm_vgic_setup_default_irq_routing:
340 * Setup a default flat gsi routing table mapping all SPIs
342 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
344 int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner);
346 #endif /* __KVM_ARM_VGIC_H */